铜互连CMP碟形缺陷及铜残留的研究

随着器件的特征尺寸越来越小,集成良越来越高,超大规模集成电路（ULSI）中设计的金属导线变细使得金属电阻增大,产生的热量增多,从而产生了严重的电迁移现象,同时由于线间电容和金属电阻增大引起的延迟（RC Delay）也不断恶化,这些都大大影响了器件的性能。传统的铝互连工艺因不能满足器件要求也逐渐被铜互连工艺取代。     

Raphael-深亚微米集成互连参数仿真优化系统

针对超深亚微米层次下的金属互连设计,使用Raphael(集成布线互连)仿真系统完成了互连寄生效应参数的提取。介绍了Raphael仿真系统的主要功能及基本应用,并分析了常规集成布线互连参数模型。采用二层跨越式互连结构,对寄生电阻、电容参数进行了仿真,并得到电流密度的分布结果。这些参数的提取及验证对电路的布局设计是十分重要的。     

微带线到共面波导的LTCC 宽带耦合互连过渡

在LTCC 多层电路结构中,不同形式的信号传输线之间往往采用垂直通孔互连,但由于互连通孔在高频时会 带来电感效应,且加工后会因变形而引入许多寄生参量,因此可选择耦合形式的互连过渡来实现不同传输线之间的互 连。本文针对微带线到共面波导,设计了一种可应用于LTCC 工艺的宽带耦合互连过渡结构,着重研究了耦合金属面 的宽度和耦合金属面侧边对地间隔对过渡结构频率特性的影响,并优化这些尺寸,得到了理想仿真结果：4.3GHz 到 12.7GHz 的频带内,回波损耗大于10dB,插入损耗最小到0.346dB,辐射损耗系数在小于12GHz 时,小于8.56%。     

RF-CMOS建模:MOST在片测试结构寄生分析

提出了一种新的RF-CMOS晶体管在片测试结构寄生模型,模型综合考虑了射频/微波条件下RF-MOST器件在片测试结构中的各种寄生效应.模型考虑了PAD-互连金属、互连金属-DUT(device under test)之间的非连续性,对互连金属和基底之间的寄生效应单独进行了考虑.通过引入一个新的元件,对PAD结构基底感性损耗进行表征.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25 μm RF-CMOS工艺制造的测试结构寄生效应等效电路建模中,高达40GHz测试和仿真数据验证了模型的良好精度.     

RF-CMOS建模:MOST在片测试结构寄生分析

提出了一种新的RF-CMOS晶体管在片测试结构寄生模型,模型综合考虑了射频/微波条件下RF-MOST器件在片测试结构中的各种寄生效应.模型考虑了PAD-互连金属、互连金属-DUT(device under test)之间的非连续性,对互连金属和基底之间的寄生效应单独进行了考虑.通过引入一个新的元件,对PAD结构基底感性损耗进行表征.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25 μm RF-CMOS工艺制造的测试结构寄生效应等效电路建模中,高达40GHz测试和仿真数据验证了模型的良好精度.     

65 nm的互连线工艺灵敏度分析

集成工艺尺寸的不断缩小使得工艺偏离效应(process variation)成为实现集成电路高成品率设计的关键.本文通过互连线工艺灵敏度分析来探讨工艺偏离效应问题.首先利用TCAD软件仿真单变量试验样本,对仿真样本数据统计3-σ值,定性分析灵敏度关系.然后用最小二乘法拟合曲线,定量分析65nm的互连线工艺灵敏度.分析结果表明互连线寄生参数随互连线宽度变化最为显著.     

RF CMOS工艺片上MOM电容的宽频带建模与验证

提出了一种新的基于RF CMOS技术的金属-氧化物-金属(MOM)电容宽频带建模方法。为了提高模型精度、扩展有效频带,模型在构造时加入了测试焊盘和输入/输出互连线的等效电路。测试结构是基于自身物理结构进行架构的,充分考虑了其在高频时引入的各种寄生效应。互连线模型考虑了高频时的趋肤效应。通过解析提取的方法,在低频时提取测试结构引入的容性和阻性寄生参数。采用物理公式计算互连线的等效电感和电阻以及高频下互连线产生的趋肤效应参数初值。对于模型拓扑结构和参数提取方法,采用40 nm RF CMOS工艺上设计所得连带测试结构MOM电容数据进行验证。在0.25～110 GHz的频率范围内,可得测试和仿真的S参数精确吻合。     

高速MCM布线网互连和封装效应的计算机仿真

本文针对高速MCM布线网中由互连和封装引起的寄生效应提出了进行计算机仿真的方法.此方法以兰召斯Pade逼近算法(PVL)为基础,综合了部分元等效电路的三维模型,微分求积法的互连线宏模型,求解包含通孔、多导体互连线和集总元件组成的复杂线网对高速脉冲信号的响应.为分析高速MCM设计中的电特性问题提供了高效的工具.     

铜互连

铜互连是指以Cu作为金属互连材料的一系列半导体制造工艺，以此克服传统工艺中采用Al作为金属互连材料在芯片尺寸越来越小时产生的信号延时增大的问题。在90nm及其以下的技术节点上，主要信号延时将来自互连电路部分。因此，选用电阻率比较小的金属互连材料和选用介电常数比较小的介电材料是降低信号延时、提高时钟频率的两个主要方向。     

铜互连电迁移失效的研究与进展

Cu/低k互连的电迁移失效与互连材料、工艺、结构和测试条件都有着密切的联系。论述了近年来铜互连电迁移可靠性的研究进展,讨论了电迁移的基本原理、失效现象及其相关机制和微效应以及主导失效的机制——界面扩散等,同时探讨了改善铜互连电迁移性能的各种方法,主要有铜合金、增加金属覆盖层及等离子体表面处理等方法,并指出了Cu互连电迁移可靠性研究有待解决的问题。     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given     

Current crowding effects and determination of specific contact resistivity from contact end resistance (CER) measurements

Current crowding effects on Contact End Resistance (CER) test structures due to the finite diffusion overlap of the contact window are studied by experiment and numerical simulation. This finite overlap adds a parasitic resistance component not accounted for by the standard one-dimensional theory, and if uncorrected, this parasitic resistance may lead to gross overestimation of the true specific contact resistivity ρc. The overestimate increases with increasing diffusion sheet resistance and large contact size. Excellent agreement between experiment and simulations has allowed this effect to be modeled. Accurate values of ρcin the range of 5 × 10^-8to 2 × 10^-5Ω cm²are extracted using CER structures.     

Parasitic modeling and noise mitigation in advanced RF/mixed-signal silicon germanium processes

The potential for highly integrated radio frequency (RF) and mixed-signal (AMS) designs is today very real with the availability cost-effective scaled silicon-germanium (SiGe) process technologies. However, the lack of effective parasitic modeling and noise mitigation significantly restrict opportunities for integration, due to a lack of computer-aided design solutions and practical guidance for designers. This tutorial paper provides a broad in-depth coverage of the key technical areas that designers need to understand in estimating and mitigating IC parasitic effects. A detailed analysis of the parasitic effects in passive devices, the interconnect (including transmission line modeling) and substrate impedance, and isolation estimation is presented-referencing a large number of key publications in these areas.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.     

An integrated improved CCII topology for resistive sensor application

In this paper a novel low voltage low power topology of second generation current conveyor (CCII) is presented. The internal CCII stages have been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. As an application example, the here proposed CCII, designed in standard CMOS technology (AMS 0.35 μm), has been used to design an integrated resistive sensor interface, showing the capability of compensating the non idealities of passive and active components. Preliminary and post-layout simulations show an excellent linearity for what concerns sensor sensitivity.     

Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints

This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.      

VLSI片上互连线电感提取技术及考虑电感效应的互连分析

VDSM工艺下，芯片的高速、高集成度趋使电磁耦合作用不容忽略；而电感效应的引入使VLSI设计和验证变得复杂，本文阐述了VLSI片上互连线电感提取技术现状及发展方向，对各类提取方法作了扼要比较；同时探讨了互连分析中包含电感效应时存在的部分问题和解决办法，以期作为提高VLSI设计、分析和验证效率的有效向导。     

A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization

CMOS differential cross-coupled LC oscillators are widely used due to their superior phase noise performance. Even though the number of circuit elements is small, the design process is not trivial due to the complicated trade-off between the phase noise and power consumption. Conventionally, cross-coupled oscillators can be constructed by using only PMOS or only NMOS devices or using both (CMOS). The topology selection is mostly based on either theoretical calculations or experimental (measurement/simulation) results on specific solution points reported in the literature; however, there is no comprehensive analysis on comparison of these topologies in the literature. Also, there are several efforts on improving the phase noise response such as conventional tail noise filtering (using a tail capacitor or LC filter) and sinusoidal tail shaping. Yet, the cost-performance effectiveness of such techniques has not been well-discussed in the literature. In this study, performances of different differential cross-coupled LC oscillators are examined using a parasitic-aware multi-objective RF circuit synthesis tool. PMOS, NMOS, and CMOS types of oscillators were synthesized and performances of those circuits were thoroughly demonstrated. The synthesis results were validated by performing post-layout simulations for different solutions located on the Pareto optimal front (POF). To observe the effect of the other layout parasitics, the CMOS oscillator was also optimized including a parasitic netlist of a drawn layout. The effect of using LC tank with centre-tapped inductor on oscillator performance was also investigated. Furthermore, effectiveness of several phase noise reduction techniques; tail capacitor filtering, tail LC filtering, and sinusoidal noise shaping were demonstrated and discussed in detail.     

Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-$ muhbox{m}$ three-dimensional (3-D)–SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D–SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D–SOI technology are also characterized and compared with conventional bulk CMOS technology.