Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

Programmable unijunction transistor for integrated circuits

There are a limited number of components that may be put in integrated form. By proper selection of standard components, a simulated four-layer device may be integrated to yield unijunction transistor performance. Device parameters may be determined by circuit configuration, thereby satisfying the requirements of the programmable unijunction transistor.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

An optimized output stage for MOS integrated circuits

An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data is also presented which allows a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

An experimental and theoretical analysis of double-diffused MOS transistors

An experimental and theoretical study of double-diffused MOS transistors (DMOST's) has been made. A simple, analytic two-transistor model gives insight into DMOS device physics as well as predicting DMOST characteristics. Both the model and experimental results show that three distinct regions of operation exist: short-channel control, long-channel control, and carrier velocity saturation control. Quantitative criteria are established for judging the region of operation as a function of device parameters and terminal voltages. A DMOST may be optimized to have the same d.c. characteristics as its short-channel component transistor over most of its operating range. A two-transistor model suitable for Computer-Aided Circuit Design (CAD) is also presented.     

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.     

Harmonic distortion in single-channel MOS integrated circuits

Expressions assuming a simple square-law MOSFET model are presented for the low-frequency harmonic distortion of an enhancement-mode source follower. These theoretical results are compared to measurements of several integrated versions of the three circuit types. For a given fabrication process, the main factors determining the amount of distortion for all three circuits are the quiescent output voltage and the output swing; to a first order, the distortion does not depend on bias current or device geometries. The distortion of an enhancement-mode source follower has a similar behavior to that of an enhancement-load inverter with the same output quiescent voltage and output swing; both distortions are nearly proportional to the body-effect coefficient. For the same output quiescent voltage and output swing, the distortion of the depletion-load inverter is the highest among the three circuits, but is practically independent of process parameters.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Computer generation of colored noise for time-domain analysis of integrated circuits

In many designs it is necessary to establish how noise affects the performance of the circuit under consideration. The type of noise analysis supported by most simulators is a frequency domain small-signal analysis around a DC operating point. This approach cannot be applied to circuits designed to operate in heavily nonlinear conditions. This paper presents an algorithm to generate random time-domain noise signals with a specified power density spectrum. The algorithm can be implemented easily and efficiently in a circuit simulator, and the noise signal thus generated can be used in ordinary transient analysis. Use of this algorithm is demonstrated in the analysis of the noise performance of a comparator and of an optical amplifier.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

Analogue MOS current-mode circuits for three-dimensional integrated smart image sensor

An image processing technique using analogue MOS current-mode circuits is presented. This approach is of interest in smart image sensors based on three-dimensional (or multi-layered) VLSI structures. High-performance smart image sensors with high resolution can be realised because the number of transistors required for image processing in each pixel is greatly reduced.<>     

MOS power transistor model for Electromagnetic Susceptibility analysis

This paper deals with the susceptibility of MOS power transistors to radio frequency interference. An nMOS connected in the low-side configuration is considered and the failures that result from disturbances superimposed onto the drain-source nominal signal are discussed. The susceptibility of power transistors to electromagnetic interference is analyzed referring to small-signal equivalent circuits and the influence of the gate-source input loop impedance is highlighted. To these purpose a distributed gate resistance model is used in small-signal analysis and time domain simulations. The results obtained with this model are in a much better agreement with the experimental results than those obtained with commonly used lumped models are. On the basis of these investigations some technology and design solutions are proposed to reduce the susceptibility to electro-magnetic disturbances affecting the drain-source terminals of a power MOS transistor connected in the low-side configuration.     

Accurate and efficient models for the simulation of neuron MOS integrated circuits

In this paper, we have simulated some neuron MOS analogue and digital integrated circuits by the proposed macromodels of neuron MOS transistor and complementary neuron MOS used in SPICE-based computer simulators. Both models take into account all the geometrical and electrical parameters of the studied device structure, and they are applicable to DC and transient simulations. Simulation results are presented and compared with recent experimental data.     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

A new buried-oxide isolation for high-speed high-density MOS integrated circuits

The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices.     

MOS Pass transistor turn-off transient analysis

Errors induced by turn-off transients are one fundamental limit in precision switched capacitor circuits. This paper presents detailed pass transistor turn-off transient analysis. Conventional single-lump models which assume quasi-static operation can introduce substantial errors for high-speed analog applications. New distributed and two-lump models have been constructed to analyze pass transistor turn-off transients in the diffusion mode of operation. A pass transistor test chip including a new selectively doped pass transistor approach has been designed, fabricated, and tested to verify the transient analysis. Measured performance of the nonuniformly doped pass transistors shows advantages in reducing transient charge errors.     

Small geometry MOS transistor capacitance measurement method using simple on-chip circuits

A method of measuring the gate capacitance of very small geometry devices using simple on-chip circuits is described. Short-channel effects observed in gate capacitance measurements of an MOS transistor with Weff/Leff= 9.2 µm/0.8 µm are presented. Measurement results show that the resolution of the technique is much better than 0.1 fF.