Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

采样时钟抖动在弱光信号检测中的影响分析

信号采样是弱光信号检测的关键技术环节,由于采样时钟抖动引起的采样信号的输出误差会影响后续的信号检测和处理。为此,分析了输入光信号为近高斯分布波形时由时钟抖动引起的采样误差,推导出了采样输出的信噪比损失公式,讨论了采样带宽、输入信噪比以及信号脉宽对输出信噪比损失的影响,最后以取样积分检测技术为对象,计算了在不同累积次数的条件下采样抖动对取样积分检测性能的影响,对弱光信号检测中的采样时钟选取具有一定的指导意义。     

Spatial Quantized Analog-to-Digital Conversion Based on Optical Beam-Steering

A novel optical spatial quantized analog-to-digital converter (ADC) is presented and the performance enhancements through employing this architecture are analyzed theoretically. A high-speed low-jitter ADC sampling clock is provided by a mode-locked laser. A high sampling rate is maintained by avoiding any speed-limiting conversion from optical to electrical domain in an all-optical quantization technique. A high quantization bandwidth is achieved by employing the all-optical quantization technique, benefiting from the high bandwidth characteristics of optical modulation. A high ADC resolution is obtained by using a single-channel quantization configuration and detecting a single image at each sampling step. A high power efficiency is achieved by extracting some portions of the required power from the analog electrical signal and optical sampling clock, directly. Various ADC-resolution limiting factors including the ambiguity of photodetectors, jitter of the optical sampling-clock, the limited beam deflector bandwidth, dispersion, phase modulator nonlinearity/mismatch, noise, and crosstalk have been identified and the contribution of each effect has been discussed.      

Signal Reconstruction Errors in Jittered Sampling

One of the most significant types of error in digital signal processing (DSP) systems working with wideband signals is the error introduced by the analog-to-digital (AD) and digital-to-analog (DA) converters. This paper presents an accurate and simple method to evaluate the performance of AD/DA converters affected by clock jitter, which is based on the analysis of the mean square error (MSE) between the reconstructed signal and the original one. Using an approximation of the linear minimum MSE (LMMSE) filter as reconstruction technique, we derive analytic expressions of the MSE. In particular, through asymptotic analysis, we are able to simply evaluate the performance of digital signal reconstruction as a function of the clock jitter, number of quantization bits, signal bandwidth and sampling rate.      

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.     

Coding, decoding, and recovery of clock synchronization in digital multiplexing system

High-speed broadband digital communication networks rely on digital multiplexing technology where clock synchronization, including processing, transmission, and recovery of the clock, is the critical technique. This paper interprets the process of clock synchronization in multiplexing systems as quantizing and coding the information of clock synchronization, interprets clock justification as timing sigma-delta modulation (T/spl Delta/-/spl Sigma/M), and interprets the jitter of justification as quantization error. As a result, decreasing the quantization error is equivalent to decreasing the jitter of justification. Using this theory, the paper studies the existing jitter-reducing techniques in transmitters and receivers, presents some techniques that can decrease the quantization error (justification jitter) in digital multiplexing systems, and presents a new method of clock recovery.     

Detailed Theoretical and Experimental Characterization of 10 Gb/s Clock Recovery Using a Q-Switched Self-Pulsating Laser

A detailed characterization of the clock recovery properties of a self-pulsating, three-section distributed feedback laser is presented by directly comparing simulation and experimental results for the dependence of the RMS timing jitter of the recovered clock signal on important properties of the input signal. These properties include the duty cycle, peak power, extinction ratio, state-of-polarization, optical signal-to-noise ratio (OSNR), and waveform distortion due to residual group velocity dispersion and polarization mode dispersion. The permissible range for each of these is identified in terms of the RMS timing jitter of the recovered clock signal being less than 2 ps. In particular, the self-pulsating laser is effective for input signals degraded by amplified spontaneous emission noise as it provides this level of jitter performance for input OSNRs larger than 8.8 dB (0.1 nm noise bandwidth).     

4-bit FLASH ADC行为级建模与仿真

基于Matlab/Simulink的平台,设计并实现了一种新型的单通道4-bit FLASH ADC行为级仿真模型,模型充分考虑到时钟抖动、失调电压、迟滞效应、比较器噪声等非理想特性,使整个系统更逼近实际电路。在输入信号为1 GHz,采样时钟频率为500 MHz时,对非理想模型进行时域及频域分析,创建的模型和系统仿真结果可为ADC系统中的误差、静态特性及动态特性研究提供借鉴。     

Analyzing the effect of the phase-jitter in the operation of second order phase-locked loops

Phase-locked loops (PLLs) are designed to extract timing signals in telecommunication networks. Noise, cross-talk, inter-symbol interference, quantization noise, and signal distortion are responsible for oscillations in the time between two successive transitions of the clock or data signal. It appears as an accidental phase modulation superposed to the original signal. This phenomenon is called timing jitter and affects the integrity of the data recovering process and, as a consequence, the error bit rate is increased. This problem has been studied by treating the jitter as a band limited noise process and tolerance masks for the jitter amplitude and frequency are recommended for several network architectures. Here, we develop a simple model with the continuous phase deviations of the clock signals considered as periodic signals in the band of the real disturbances. Comparisons with the stochastic approach are presented.     

Jitter optimization based on phase-locked loop design parameters

This paper investigates the effects of varying phaselocked loop (PLL) design parameters on timing jitter. The noise due to voltage-controlled oscillator (WO), input clock and buffering clock are considered. First, a closed-form equations are derived that relate PLL output clock jitter to parameters of a second-order PLL, i.e., damping factor and bandwidth. Then the second-order analysis is extended to a third-order PLL with inherent feedback/sampling delay. The sensitivity study clearly illustrates how to select design parameters to obtain minimum output jitter. To verify the analysis experimentally, a digitally tunable PLL architecture is designed and fabricated that allows independent adjustment of loop parameters. The design not only demonstrates the agreement between analysis and theory, but also shows an architecture that minimizes jitter.     

Analysis of First-Order Anti-Aliasing Integration Sampler

Performance of the first-order anti-aliasing integration sampler used in software-defined radio (SDR) receivers is analyzed versus all practical nonidealities. The nonidealities that are considered in this paper are transconductor finite output resistance, switch resistance, nonzero rise and fall times of the sampling clock, charge injection, clock jitter, and noise. It is proved that the filter is quite robust to all of these nonidealities except for transconductor finite output resistance. Furthermore, linearity and noise performances are all limited to design of a low-noise and highly linear transconductor.      

可重构RF采样接收机中时钟抖动的影响

对可重构直接RF采样接收机(RDRFR)及相关技术进行了研究与分析。脉冲采样下变频技术在RDRFR接收机中起着至关重要的作用,其主要影响因子是时钟抖动。理论推导和仿真分析了时钟抖动对接收系统信噪比的影响,对比分析了RDRFR接收机与直接RF采样接收机信噪比的不同,仿真结果表明RDRFR接收机中其信噪比随输入频率的增加呈阶梯递减的趋势,并且随着采样频率的增加信噪比恶化愈严重。     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

时钟抖动对中频线性调频采样及脉冲压缩影响的研究

时钟抖动是模数转换过程中影响信号信噪比的最主要因素之一。该文从时域连续信号角度出发,按照高斯随机过程模型,分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。结合量化噪声的影响,可定量计算影响信噪比各因素之间的关系。仿真结果表明适用于模数转换后所得离散数字信号信噪比计算。合成孔径雷达经过脉冲压缩得到图像,为了抑制旁瓣需要使用窗函数加权,分析了时钟抖动在加窗前后对脉冲压缩时峰值旁瓣比和积分旁瓣比的影响。最后讨论了一些减小时钟抖动的具体措施。     

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 $muhbox{m}$ CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.      

Performance analysis of general charge sampling

This brief focuses on the performance analysis of general charge-sampling circuits for signal capture. The theoretical analysis in the brief can be applied not only for weak signal capture, but also for the normal signal sampling. Based on a general charge-sampling model, the transfer function, the noise performance, and the clock jitter tolerance are analyzed and compared to conventional voltage sampling. The results provide a theoretical basis for charge-sampling circuit design.     

Additive noise and jitter performance analysis of passive optical interferometers operated at ultrahigh rates

In this paper, we theoretically associate the additive noise, the amplitude jitter and the timing jitter at the input and output of passive optical interferometers. We make use of the theoretical results to assess the noise and jitter performance of interferometer based applications such as pulse repetition frequency multiplication and clock recovery. We show that, for both applications, interferometers may successfully reduce the noise and the jitter existing in the input signals, and thus yield very high quality output signals. Furthermore, we focus on the practical aspects of deploying Fabry-Pe/spl acute/rot interferometers in rate multipliers and clock recoveries, and provide rules for selecting the characteristics of the Fabry-Pe/spl acute/rot interferometer to meet specific quality requirements for the output signal.     

基于AD9208的高速采集电路设计

针对大带宽采样需求,设计了基于AD9208的高速采集电路,通过分析时钟抖动,噪声等因素对采集电路的影响,设计了相关电路,包括低抖动时钟电路、模拟信号输入电路、电源电路,并测试了在不同输入频率下,AD9208的无杂散动态范围.