MPEG-2视频反量化电路的VHDL描述与验证

设计了用于ＭＰＥＧ－２ＭＰ＠ＭＬ视频解码ＶＬＳＩ的ＩＱ电路结构,基于对ＩＱ的运算字长和精度关系的分析,有针对性地提出相应的硬件电路结构设计,减少了电路规模以适应ＭＰＥＧ－２ＭＰ＠ＭＬ视频较大的数据量,电路采用了ＶＨＤＬ进行描述并通过模拟和验证。结果表明该电路可以完成ＭＰＥＧ－２解码的功能。     

MPEG2视频解码器VLSI结构研究

介绍了ＭＰＥＧ２视频解码器的ＶＬＳＩ实现方法，采用ＡＳＩＣ结构实现ＭＰＥＧ２标准的视频解码，用流水线哈佛结构ＲＩＳＣ型微控制器对视频数据流、变字长解码以及电路时序进行控制，提高了电路速度，减小了芯片面积。     

适用于MPEG2标准的二种VLSI模块设计

本文提出了ＭＰＥＧ２视频解码器主要功能模块的专用ＶＬＳＩ结构．其中包括一种新的适用于ＭＰＥＧ２标准的ＩＤＣＴ实现方法，对于８点一维ＩＤＣＴ，只用７个变量乘常系数乘法器和１０个加／减法器，在４个时钟周期内能处理完８点数据；通过合理分配画面存储结构，提出了一种新的流水线的运动补偿预测结构．用ＶＨＤＬ语言进行仿真，并用１．０μｍＣＭＯＳ单元库进行综合，满足ＭＰＥＧ２ＭＰ＠ＭＬ视频解码的实时处理要求     

MPEG—2视频IDCT的VHDL描述与验证

反离散余弦变换是ＭＰＥＧ－２中恢复帧内编码系数或差分系数的重要手段。３设计了用于ＭＰＥＧ－２ＭＰ＠ＭＬ视频解码ＶＬＳＩ的ＩＤＣＴ电路结构,采用了ＶＨＤＬ进行描述并通过模拟和验证。这里采用了全硬件实现的方法,并针对性地提出相应的硬件电路结构设计,减少了电路规模以适应ＭＰＥＧ－２ＭＰ＠ＭＬ视频量大,处理复杂的特点,达到实进解码的目的。     

MPEG—2解码硬件的实现

本文介绍了ＬＳＩ ＬＯＧＩＣ公司芯片Ｌ６４００７，Ｌ６４００２作为主芯片的ＭＰＥＧ－２系统／视频／音频解码系统，分析了传输液的句法结构；并根据实际工作遇到的技术难点，着重讨论了了解复用模块中的时钟恢复以及视频与音频的同步播放。     

MPEG-2视频码流分解的VHDL描述与验证

本文提出一个ＭＰＥＧ－２视频解码中码流分解的硬件设计,包括解码控制和变长码解码。一些新的硬件设计,如：将宏块和块控制作为主要状态;采用桶形移位缓冲器并行解变长码;将变长码的长度计算和解码分别进行;将码表分割成多个小码表等等,保证ＭＰＥＧ－２ＭＰ＠ＭＬ的实时解码,并为更复杂的应用提供了扩展的余地。本文中的设计是ＭＰＥＧ－２解码ＡＳＩＣ ＶＬＳＩ设计工作的一部分。     

MPEG—2：MPaML视频解码的硬件实现——IBM MPEG—2视频解码芯片简介

介绍ＩＢＭ公司采用ＣＭＯＳ－５Ｌ、０．５ｕｍａ３．３Ｖ技术开发的ＭＰＥＧ－２视频解码芯片的内部结构原理、功能及应用前景。     

用于满足音频和视频MPEG标准的LSI芯片

本文介绍了一些满足音频和视频ＩＳＯ／ＩＥＣ ＭＰＥＧ标准的编译码芯片。这些芯片是由ＮＥＣ公司在最近二年内设计制造的。为了满足ＭＰＥＧ１视频标准的需要，ＮＥＣ公司开发了这组用于编译码器设计的芯片。这些芯片可分为三类，其中二类用于译码器的设计，另一类则用于实时ＭＰＥＧ１编码器的设计。同时还使用了一个可编程处理器以支持ＬＴＵ－ＴＨ．２６１和ＪＰＥＧ标准。为支持ＭＰＥＧ２视频标准专门开发了一组译码芯片，它     

MPEG－2：MPaML视频解码的硬件实现──IBM MPEG－2视频解码芯片简介

介绍ＩＢＭ公司采用ＣＭＯＳ－５Ｌ、０．５μｍ３．３Ｖ技术开发的ＭＰＥＧ－２视频解码芯片的内部结构原理、功能及应用前景。     

VBR MPEG—2视频编码器的实时实现

文章在分析了ＩＢＭ公司最新的ＭＰＥＧ２视频编码专用芯片ＭＰＥＧＳ４∶２∶０芯片支持ＶＢＲ视频编码的特性,针对这些特性设计了ＶＢＲ视频编码比特率控制算法,同时,阐述了如何利用ＭＰＥＧＳ４∶２∶０,配合可编程逻辑器件和ＤＳＰ芯片,实现ＡＴＭ信道中可变比特率ＭＰＥＧ２视频编码器。     

IO单元自动排布算法IOAP

提出了一种应用于芯片物理设计过程中IO单元自动排布的新算法。IO单元排布是芯片物理设计过程中长期依赖经验的环节。IO单元排布的优化对布线,电源网格和设计收敛性的优化有很大贡献。文章重点研究边缘IO单元排布,提出了IO单元自动排布算法(IOAP)。此算法及其相关软件直接应用于视频解码芯片和无线传感器网络处理器芯片(已流片成功)的物理设计流程中。结果表明,IOAP有效改善了芯片的电源网格,时序和布线结果,减少了布线努力,提高了设计收敛性。     

A joint encoder–decoder error control framework for stereoscopic video coding

Stereoscopic video coding (SSVC) plays an important role in various 3D video applications. In SSVC, robust stereoscopic video transmission over error-prone networks is still a challenge problem to be solved. In this paper, we propose a joint encoder–decoder error control framework for SSVC, where error-resilient source coding, transmission network conditions, and error concealment scheme are jointly considered to achieve better error robustness performance. The proposed joint encoder–decoder error control framework includes two parts: an error concealment algorithm at the decoder side and a rate–distortion optimized error resilience algorithm at the encoder side. For error concealment at the decoder side, an overlapped block motion and disparity compensation based error concealment scheme is proposed to adaptively utilize inter-view correlations and temporal correlations. For error resilience at the encoder side, first, the inter-view refreshment is proposed for SSVC to suppress error propagations. Then, an end-to-end distortion model for SSVC is derived, which jointly considers the transmission network conditions, inter-view refreshment, and error concealment tools at the decoder side. Finally, based on the derived end-to-end distortion model, the rate–distortion optimized error resilience algorithm is presented to adaptively select inter-view, inter- or intra-coding for SSVC. The experimental results show that the proposed joint encoder–decoder error control framework has superior error robustness performance for stereoscopic video transmission over error-prone networks.     

Real-time video decoding scheme for HDTV set-top boxes

We present a scheme for real-time digital HDTV video decoding suitable for DVB or ATSC set-top boxes. Our technique is based on a dual decoding datapath controlled in two fixed-scheduling combinations with an efficient memory interface scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on a video format of 1920 /spl times/ 1080 pixels/frame at 30 frames/s, at a bit rate of 18-22 Mbps.     

Adaptive chaining scheme for distributed VOD applications

In distributed video on demand (VOD) applications, a client station buffers a shifting window of its displaying video so that the video stream can be chained from the client to another one arriving within the window, instead of consuming a server stream for each new request. This scheme is called video chaining that can reduce the load of video servers significantly. In this paper, we propose a novel adaptive chaining scheme that extends the basic chaining scheme with two new techniques: two-way bridging and multicast chaining. The two-way bridging method employs video buffers as forward and/or backward bridges to extend each video chain as long as possible. It provides nearly twice the performance gain than basic chaining in terms of server I/O load reduction. Mathematical analyses for both schemes are also given. The multicast chaining method maximizes the multicast degree of each video chain so that lower data delivery cost per video session can be achieved. Our scheme maintains the video chains optimally to shift the load to active clients so that the I/O bottleneck of video servers is released     

SAA7115视频解码芯片寄存器的配置与应用

为确保视频传输过程中传输数据的正确性,设计了一个简单的视频信号传输系统。在该系统中,对视频解码芯片的配置很关键。与其它普通视频解码芯片相比,SAA7115解码芯片内有自适应的NTSC/PAL/SECAM制式的梳状滤波器,具有高性能图像缩放及I2C总线Read back技术、适用范围广,因此视频解码芯片选用SAA7115。并对SAA7115视频解码芯片中的一些关键寄存器进行了特殊配置,对采集的数据进行了实时显示。结果表明,在该配置下保证了解码数据的正确性,并实现了实时传输。     

MPEG2专用视频解码VLSI中的控制策略

本文提出了一种新的适用于MPEG2专用视频解码芯片的控制策略：分散控制。该方案完全由各功能模块相互协调控制整个视频解码过程，而不需要总体控制，它满足对MPEG2视频规定的所有级别尤其是MP@HL进行实时解码的要求。与总体控制方式比较，分散控制机制对视频解码各功能模块没有严格的时间限制，可根据具体解码任务特性设计模块从而达到局部性能最优；同时分散控制过程简单，解码效率高，而且连接各功能模块间的缓存相当小，可大幅度的减小芯片的硬件开销，使得系统整体性能最优。     

Perceptual-based distributed video coding

In this paper, we propose a perceptual-based distributed video coding (DVC) technique. Unlike traditional video codecs, DVC applies video prediction process at the decoder side using previously received frames. The predicted video frames (i.e., side information) contain prediction errors. The encoder then transmits error-correcting parity bits to the decoder to reconstruct the video frames from side information. However, channel codes based on i.i.d. noise models are not always efficient in correcting video prediction errors. In addition, some of the prediction errors do not cause perceptible visual distortions. From perceptual coding point of view, there is no need to correct such errors. This paper proposes a scheme for the decoder to perform perceptual quality analysis on the predicted side information. The decoder only requests parity bits to correct visually sensitive errors. More importantly, with the proposed technique, key frames can be encoded at higher rates while still maintaining consistent visual quality across the video sequence. As a result, even the objective PSNR measure of the decoded video sequence will increase too. Experimental results show that the proposed technique improves the R-D performance of a transform domain DVC codec both subjectively and objectively. Comparisons with a well-known DVC codec show that the proposed perceptual-based DVC coding scheme is very promising for distributed video coding framework.     

Cross-band noise model refinement for transform domain Wyner-Ziv video coding

Distributed Video Coding (DVC) is a new video coding paradigm, which mainly exploits the source statistics at the decoder based on the availability of decoder side information. One approach to DVC is feedback channel based Transform Domain Wyner-Ziv (TDWZ) video coding. The efficiency of current TDWZ video coding trails that of conventional video coding solutions, mainly due to the quality of side information, inaccurate noise modeling and loss in the final coding step. The major goal of this paper is to enhance the accuracy of the noise modeling, which is one of the most important aspects influencing the coding performance of DVC. A TDWZ video decoder with a novel cross-band based adaptive noise model is proposed, and a noise residue refinement scheme is introduced to successively update the estimated noise residue for noise modeling after each bit-plane. Experimental results show that the proposed noise model and noise residue refinement scheme can improve the rate-distortion (RD) performance of TDWZ video coding significantly. The quality of the side information modeling is also evaluated by a measure of the ideal code length.     

OFDM系统中视频传输的调度算法研究

针对OFDM系统,提出了一种基于视频内容的跨层调度方案。该方案采用了基于生存期的包排序策略,根据视频包的生存期大小进行排序,保证视频包能在生存期内发送到接收端,减少丢包数目。同时,采用跨层设计的思想,综合考虑了信道状况和视频包特性,如视频包生存期、重要性、解码器采用的错误掩藏方法,提出改进的比例公平调度算法,不仅有效地利用了多用户分集来进一步提高数据吞吐量,也充分考虑了视频的重要性和时延约束。实验结果表明,采用内容感知的跨层调度算法,解码端的视频质量得到有效提高,从而可以提高主观感知质量。     

网内编码：无线视频传感网中分布式编码速率控制机制

Wyner-Ziv Video Coding (WZVC) is considered as a promising video coding scheme for Wireless Video Sensor Networks (WVSNs) due to its high compression efficiency and error resilience functionalities, as well as its low encoding complexity. To achieve a good Rate-Distortion (R-D) performance, the current WZVC paradigms usually adopt an end-to-end rate control scheme in which the decoder repeatedly requests the additional decoding data from the encoder for decoding Wyner-Ziv frames. Therefore, the waiting time of the additional decoding data is especially long in multihop WVSNs. In this paper, we propose a novel progressive in-network rate control scheme for WZVC. The proposed in-network puncturing-based rate control scheme transfers the partial channel codes puncturing task from the encoder to the relay nodes. Then, the decoder can request the additional decoding data from the relay nodes instead of the encoder, and the total waiting time for decoding Wyner-Ziv frames is reduced consequently. Simulation results validate the proposed rate control scheme.