Normally On/Off Integrated Latching Acceleration Switch With Controlled Fracture Beams and Independent Multicontact

This letter reports an acceleration latching switch with integrated normally on/off paths. The normally on path, formed by notched beams connected in series, will be broken and latched to reach the open state when the acceleration exceeds the threshold. A multicontact is adopted for the normally off path, while both paths are mechanically separated from the proof mass to prevent them from the impact of the proof mass at the latched state. Experimental results show that the latching shock is 10 000 G, and the response time is about 0.1 ms. The normally on path has an on-state resistance of 4.0 $Omega$ and an allowable current of 200 mA, whereas the normally off path has an on-state resistance of 3.8 $Omega$ and a maximum current of 140 mA.      

A High-Performance Polysilicon Thin-Film Transistor Built on a Trenched Body

In this paper, a high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is proposed, fabricated, and studied. This new trenched TFT can be easily produced by filling and etch-back technology without destroying the channel film quality. The addition of the body trench is found to reduce the off-state leakage current by 70% on average, because the trench induces a carrier scattering effect in the poly-Si grain-boundary traps, thereby affecting the leakage path. Although the off-state current is substantially reduced, the on-state current is comparable with that of a conventional TFT. Our multiple-trenched-body TFT is also shown to improve the breakdown voltage by 11%.      

Vacancy Generation by Laser Preirradiation for Junction Leakage Suppression

Vacancy generation by laser preirradiation on silicon substrate before implantation for advanced junction engineering was demonstrated. Amorphized $hbox{p}^{+}/hbox{n}$ junction diodes subjected to preimplant laser irradiation show a twofold reduction on the off-state leakage current and a two-time improvement on the on-state current compared to control devices without any preirradiation. The defect-removal mechanism is achieved by the recombination of excess vacancies trapped at the maximum laser melt depth as a result of the molten silicon recrystallization with the implantation-generated interstitials. The effectiveness of laser-generated vacancies in annihilating residual defects is evident in the suppression of junction leakage current.      

A Novel Discrete Dimming Ballast for Linear Fluorescent Lamps

A novel discrete dimming ballast for linear fluorescent lamps is proposed in this paper. A proposed dimming control circuit is combined with a ballast module for multiple lamps to realize control of three discrete lighting levels. Compared with conventional step dimming or on– off control methods, the proposed discrete dimming method has the following advantages: 1) digital signal is generated by the dimming control circuit to control the lamps' turn- on and -off, which makes the system more reliable and integrated; 2) the proposed discrete dimming system replaces relays, which are necessary in conventional lamp on–off control, and therefore decreases the system cost; 3) the proposed dimming ballast can be installed by keeping the original wiring system. This makes the upgrading of a lighting system more effective and efficient; 4) the dimming control circuit also provides a good isolation for operating the low-voltage wall switches by hand safely. Both theoretical, simulation, and experimental results are in good agreement.      

Improved Electrical Performance and Uniformity of MILC Poly-Si TFTs Manufactured Using Drive-In Nickel-Induced Lateral Crystallization

A new manufacturing method for polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using drive-in nickel-induced lateral crystallization (DILC) was proposed. In DILC, a $ hbox{F}^{+}$ implantation was used to drive Ni in the $alpha$ -Si layer. To reduce Ni contamination, the remained Ni film was then removed and subsequently annealed at 590 $^{circ}hbox{C}$. It was found that DILC TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high on-state current, lower trap-state density, smaller standard deviations, and low off-state leakage current compared with conventional Ni-metal-induced lateral crystallization TFTs.      

Investigation of the Suitability of 1200-V Normally-Off Recessed-Implanted-Gate SiC VJFETs for Efficient Power-Switching Applications

A recessed-implanted-gate (RIG) 1290-V normally-off (N-OFF) 4H–SiC vertical-channel JFET (VJFET), fabricated with a single masked ion implantation and no epitaxial regrowth, is evaluated for efficient power conditioning applications. The relationship between the VJFET's on-state resistance and current gain is elucidated. Under high-current-gain operation, which is required for efficient power switching, the 1200-V N-OFF (enhancement mode) VJFET exhibits a prohibitively high on-state resistance. Comparison with 1200-V normally-on VJFETs, fabricated on the same wafer, confirms experimentally that the strong gate-depletion-region overlap required for 1200-V N-OFF blocking is the principal contributor to the prohibitively high specific on-state resistance observed under high-current-gain VJFET operation. Perfecting the 1200-V edge termination structure, which can reduce the theoretical drift specific on-state resistance from 2.2 to 1.5 $hbox{m}Omega cdot hbox{cm}^{2}$, has a negligible impact in decreasing the channel-dominated 1200-V N-OFF VJFET resistance. The RIG VJFET channel-region optimization simulations (assuming a single commercial implantation and no epitaxial regrowth) revealed that, although aggressively increasing channel doping lowers the resistance, the corresponding reduction in the source mesa width can prohibitively limit manufacturability.      

Graphene Nanoribbon Tunnel Transistors

A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 $muhbox{A}/muhbox{m}$ on -state current and 26 $hbox{pA}/muhbox{m}$ off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 $n$MOSFET, the GNR TFET can provide 5$times$ higher speed, 20$ times$ lower dynamic power, and 280 000$times$ lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.      

Write-Once Read-Many-Times Memory Based on a Single Layer of Pentacene

We realized an organic electrical memory device with a simple structure based on single-layer pentacene film embedded between Al and ITO electrodes. The optimization of the thickness and deposition rate of pentacene resulted in a reliable device with an on/off current ratio as high as nearly $ hbox{10}^{6}$, which was two orders of magnitude higher than previous results, and the storage time was more than 576 h. The current transition process is attributed to the formation and damage of the interface dipole at different electric fields, in which the current conduction showed a transition from ohmic conductive current to Fowler–Nordheim tunneling current. After the transition from on - to off-state, the device tended to remain in the off-state even when the applied voltage was removed, which indicated that the device was very promising for write-once read-many-times memory.      

Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

The impact of scaling the depth of the shallow trench isolation (STI) region, underneath the gate-to-drain overlap, on the STI drain-extended metal–oxide–semiconductor (DeMOS) mixed-signal performance and hot-carrier behavior is systematically investigated in this work. For the first time, we discuss a dual-STI process for input/output applications. Furthermore, the differences in the hot-carrier behavior of various drain-extended devices are studied under the on- and off-states. We found that the non-STI DeMOS devices are quite prone to failure when compared with the STI DeMOS devices in both the on- and off- states. We introduced a more accurate way of predicting hot-carrier degradation in these types of devices in the on-state. We show that scaling the depth of the STI underneath the gate is the key for improving both the mixed-signal and hot-carrier reliability performances of these devices.      

The Nanoscale Silicon Accumulation-Mode MOSFET—A Comprehensive Numerical Study

Recently, we proposed and experimentally demonstrated a very simply structured unipolar accumulation-type field-effect transistor (FET) using silicon nanowires (NWs). In this paper, we present an extensive numerical study of this accumulation metal–oxide–semiconductor FET (AMOSFET). This single-doping-type ohmically contacted structure relies on having a nanoscale dimension normal to the gate, thereby forcing the current path through an accumulated (on-state) or depleted ( off-state) region. It also relies on having contact-barrier and doping-dependent minimum source and drain lengths as well as minimum gate lengths to insure unipolar transistor action. The comprehensive report presented extends our previous examination of the device's operation by using extensive numerical simulations to offer a greater understanding of the origins of transistor operation. We explore a wide range of structural and material parameters to study their effects on the linear, saturation, and off-state currents. We also delve deeper into the uniquely weak dependence on gate capacitance. This paper establishes that this extremely simple accumulation-mode transistor structure offers its best performance for the more highly doped thinnest devices, giving, for example, for a $hbox{10}^{17}hbox{-}hbox{cm}^{-3}$ (doping) and 20-nm device a leakage current of $sim!!hbox{10}^{-17} hbox{A}/muhbox{m}$ , a subthreshold swing of 65 mV/dec, and an on–off ratio approximately $hbox{10}^{10}$. This paper also shows that such results should be attainable for AMOSFETs fabricated using NWs and nanoribbons, as well as nanoscale thin-film mate- - rial     

Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the off-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high off-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.      

Switching Time in Relaxation Oscillations of Emitter-Coupled Multivibrators

This paper gives an estimation of the switching time between on and off transistor states for the emitter-coupled multivibrator. The calculation uses the root locus of the characteristic equation for the oscillator small-signal equivalent circuit, while changing the device current as a parameter. The switching time is found using a fitting location of the root in the right half of the $s$-plane. The oscillation frequency is also obtained. The approach provides a further insight into switching behavior of relaxation oscillators, gives an accurate estimation of the oscillation frequency, and allows one to establish a useful connection between sinusoidal and relaxation oscillators. The theoretical results are confirmed by simulations.      

Novel TCAD-Oriented Definition of the off-State Breakdown Voltage in Schottky-Gate FETs: A 4H–SiC MESFET Case Study

Physics-based breakdown voltage optimization in Schottky-barrier power RF and microwave field-effect transistors as well as in high-speed power-switching diodes is today an important topic in technology computer-aided design (TCAD). off-state breakdown threshold criteria based on the magnitude of the Schottky-barrier leakage current can be directly applied to TCAD; however, the results obtained are not accurate due to the large uncertainty in the Schottky-barrier parameters and models arising above all in advanced wide-gap semiconductors and to the need of performing high-temperature simulations to improve the numerical convergence of the model. In this paper, we suggest a novel off-state breakdown criterion, based on monitoring the magnitude (at the drain edge of the gate) of the electric field component parallel to the current density. The new condition is shown to be consistent with more conventional definitions and to exhibit a significantly reduced sensitivity with respect to physical parameter variations.      

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 $mu hbox{m}$ exhibits a BV of 500 V and specific on-resistance $(R_{{rm on}, {rm sp}}!)$ of 96 $hbox{m}Omega cdot hbox{cm}^{2}$, yielding to a power figure of merit $(BV^{2}!!/ !R_{{rm on}, {rm sp}})$ of 2.6 $hbox{MW}/hbox{cm}^{2}$ . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.      

AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio

In this letter, we propose using an oxide-filled isolation structure followed by $hbox{N}_{2}/hbox{H}_{2}$ postgate annealing to reduce the leakage current in AlGaN/GaN HEMTs. An off-state drain leakage current that is smaller than $hbox{10}^{-9} hbox{A/mm}$ (minimum $hbox{5.1} times hbox{10}^{-10} hbox{A/mm}$) can be achieved, and a gate leakage current in the range of $hbox{7.8} times hbox{10}^{-10}$ to $hbox{9.2} times hbox{10}^{-11} hbox{A/mm}$ ($V_{rm GS}$ from $-$10 to 0 V and $V_{rm DS} = hbox{10} hbox{V}$) is obtained. The substantially reduced leakage current results in an excellent on/off current ratio that is up to $hbox{1.5} times hbox{10}^{8}$. An improved flicker noise characteristic is also observed in the oxide-filled devices compared with that in the traditional mesa-isolated GaN HEMTs.      

Optimization of on-State and Switching Performances for 15–20-kV 4H-SiC IGBTs

The 4H-SiC p-channel IGBTs designed to block 15 and 20 kV are optimized for minimum loss ( on-state plus switching power) by adjusting the parameters of the $hbox{p}$ JFET region, $ hbox{p}-$ drift layer, and $hbox{p}+$ buffer layer, using 2-D MEDICI simulations. Switching loss exhibits a strong dependence on buffer layer thickness, doping, and lifetime due to their influence on the current tail. In contrast, drift layer lifetime has little effect on the crossover frequency at which the MOSFET and IGBT have equal loss.      

ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

We demonstrate ACCNT (pronounced as “accent”), a solution to the metallic-nanotube problem that does not require any metallic-nanotube removal of any kind. ACCNT uses asymmetrically correlated carbon nanotubes to achieve metallic-nanotube tolerance, delivering high on– off ratios $(hbox{10}^{4}{-} hbox{10}^{6})$ while preserving the current drive. In addition, this metallic-nanotube tolerance can be engineered arbitrarily close to 100%. We present the ACCNT concepts in detail, verifying the concepts and underlying assumptions via experimental results. We further demonstrate inverters using ACCNT and ACCNT scalability to a wafer scale. ACCNT marks the first demonstration of a VLSI-compatible metallic-nanotube-tolerant design methodology.      

Advanced High-Voltage 4H-SiC Schottky Rectifiers

This paper presents advanced 4H-SiC high-voltage Schottky rectifiers with improved performance when compared to conventional 4H-SiC Schottky rectifiers. Two types of 4H-SiC junction barrier Schottky (JBS) rectifiers have been explored. These rectifiers offer Schottky-like ON-state and fast switching characteristics, while their OFF-state characteristics have a low leakage current similar to that of the PiN junction rectifier. Planar 4H-SiC JBS rectifiers, with more than 1-kV blocking capability and orders of magnitude lower reverse leakage current than that of conventional SiC Schottky rectifiers, have been demonstrated. In addition, a novel device structure, called lateral channel JBS rectifier, was designed and experimentally demonstrated in 4H-SiC with up to 1.5-kV blocking capability and pinlike reverse characteristics.      

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the off -state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.      

Mitigation of XPM Penalty in 10-Gb/s OOK/DBPSK Mixed Modulation Format 50-GHz-Spaced WDM Transmission by Conversion of OOK to BPSK Using an SOA

Copropagation of return-to-zero differential binary phase-shift keying (RZ-DBPSK) with RZ on–off keying (RZ-OOK) in wavelength-division-multiplexed (WDM) transmission has been found to be detrimental to RZ-DBPSK due to cross-phase modulation (XPM) degradations induced by pattern-dependent RZ-OOK. A method is proposed at the optical cross-connect (not at the transmitter end) to alleviate this degradation, in which the impairing RZ-OOK channel is converted to RZ binary phase-shift keying (RZ-BPSK) in a semiconductor optical amplifier (SOA) prior to 50-GHz-spaced WDM transmission. The data format conversion completely compensates for the XPM degradation, while resulting in an optical signal-to-noise ratio transmission penalty of ${≪}$ 2 dB for converted RZ-BPSK relative to RZ-OOK. Moreover, the wavelength conversion may be used to address contention resolution at the cross-connects.