一种基于代谢路径构建系统发生树的有效方法

构建系统发生树是研究物种起源和演化的重要手段.本文基于KEGG(Kyoto Encyclopedia of Genes and Genomes)代谢路径,引入图论的"核"概念,提出一种构建系统发生树的方法.首先解决在无数据丢失前提下,代谢路径数据的提取和表示问题,其次将不同代谢路径的相似度定义为图的核部分与非核部分各自匹配程度的加权之和,利用距离矩阵构建物种间的系统发生树.通过大量试验数据和NCBI(National Center for Biotechnology Information)分类法进行比较,验证了本文方法的有效性.     

Multistate Block Diagrams and Fault Trees

This paper shows how to model a multistate system with multistate components using binary variables. This modeling technique allows current binary algorithms for block diagrams and fault trees to be applied to multistate systems. Several multistate examples are presented, and some cases in which computational efficiency can be enhanced are discussed.     

改进的地图匹配算法研究

文中研究了地图匹配技术在GPS/DR组合导航系统中的作用,分析了影响地图匹配精度的因素,模拟一种基于模糊逻辑思想的地图匹配算法。该算法通过方向性、路段的接近程度和相似性三个方面进行模糊综合评判,并且结合道路网络的拓扑结构,挑选出最佳匹配路段。仿真结果验证了该算法的有效性。     

一种有效的后缀树建立方法

基于自顶向下的后缀树建立思想,提出一种分步建立后缀树的方法。首先对字符串中所有后缀按照字母表顺序进行排序,然后求出有序相邻后缀之间的最长公共前缀,并根据后缀顺序和最长公共前缀建立后缀树。该方法无需使用后缀链,并且可以在线性时间建立后缀树。     

An Efficient Logic Equivalence Checker for Industrial Circuits

We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence. The complimentary strengths of the two types of algorithms result in a significant reduction in CPU time. Our methods also involve analytical and empirical heuristics whose impact on performance for industrial designs is considerable. The combination of OBDDs, ATPG, and our heuristics resulted in a decrease in CPU time of up to 80% over OBDDs alone for the circuits we tested. In addition, we describe an algorithm for automatically determining the correspondence between storage elements in the designs being compared.     

An Efficient Method to Synthesize Reversible Logic by Using Positive Davio Decision Diagrams

Reversible logic is a key technique for quantum computing leading to quantum communication and quantum computer. However, the bottleneck of low efficiency in the synthesis procedure limits applications of reversible logic and cannot obtain optimized reversible circuits. In this paper, an efficient method based on positive Davio expansion to synthesize reversible circuits is proposed, which generates a positive Davio decision diagram for a logic function and transfers diagram nodes to reversible circuits. A matching template is given to help nodes transformation. The experimental results prove that compared with other synthesis methods, the proposed method can obviously optimize quantum cost and keep very short execution time.     

An Efficient Approach to On-Chip Logic Minimization

Boolean logic minimization is being applied increasingly to a new variety of applications that demand very fast and frequent minimization services. These applications typically have access to very limited computing and memory resources, rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can execute with a data memory as little as 16 KB. We also found that the proposed approach can support up to 25000 incremental updates per second. We also compare its performance for compaction of the routing access control list and demonstrate that the proposed approach is highly suitable for minimizing large access control lists containing several thousand entries. Therefore, the algorithm is ideal for on-chip logic minimization.     

An Efficient Scheme for Processing Arbitrary Lumped Multiport Devices in the Finite-Difference Time-Domain Method

Developing full-wave simulators for high-frequency circuit simulation is a topic many researchers have investigated. Generally speaking, methods invoking analytic pre-processing of the device's V-I relations (admittance or impedance) are computationally more efficient than methods employing a numerical procedure to iteratively process the device at each time step. For circuits providing complex functionality, two-port or possibly multiport devices whether passive or active, are sure to appear in the circuits. Therefore, extensions to currently available full-wave methods for handling one-port devices to process multiport devices would be useful for hybrid microwave circuit designs. In this paper, an efficient scheme for processing arbitrary multiport devices in the FDTD method is proposed. The device's admittance is analytically pre-processed and fitted into one grid cell. With an improved time-stepping expression, the computation efficiency is further increased. Multiport devices in the circuit can be systematically incorporated and analyzed in a full-wave manner. The accuracy of the proposed method is verified by comparison with results from the equivalent current-source method and is numerically stable     

An Efficient FFT Engine With Reduced Addressing Logic

In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 $N$-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 $mu{rm m}$ technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.      

An Efficient Bottom-up Algorithm for Enumerating Minimal Cut Sets of Fault Trees

The paper improves the conventional bottom-up algorithm for enumerating minimal cut sets of fault tree. It is proved that, when the logical product of two reduced sum-of-product forms is expanded by the distribution rule, one need only check if each resulting term is absorbed by some terms of two original sum-of-product forms. The algorithm for executing this process is presented and illustrated by an example. The entire computer program is given in a supplement and the computational results for several examples are presented to demonstrate the efficiency of the algorithm.     

An Efficient Method for Evaluating Complex Polynomials

We propose an efficient hardware-oriented method for evaluating complex polynomials. The method is based on solving iteratively a system of linear equations. The solutions are obtained digit-by-digit on simple and highly regular hardware. The operations performed are defined over the reals. We describe a complex-to-real transform, a complex polynomial evaluation algorithm, the convergence conditions, and a corresponding design and implementation. The latency and the area are estimated for the radix-2 case. The main features of the method are: the latency of about m cycles for an m-bit precision; the cycle time independent of the precision; a design consisting of identical modules; and digit-serial connections between the modules. The number of modules, each roughly corresponding to serial-parallel multiplier without a carry-propagate adder, is 2(n?+?1) for evaluating an n-th degree complex polynomial. The method can also be used to compute all successive integer powers of the complex argument with the same latency and a similar implementation cost. The design allows straightforward tradeoffs between latency and cost: a factor k decrease in cost leads to a factor k increase in latency. A similar tradeoff between precision, latency and cost exists. The proposed method is attractive for programmable platforms because of its regular and repetitive structure of simple hardware operators.     

Fast and Efficient Method for Fire Detection Using Image Processing

Conventional fire detection systems use physical sensors to detect fire. Chemical properties of particles in the air are acquired by sensors and are used by conventional fire detection systems to raise an alarm. However, this can also cause false alarms; for example, a person smoking in a room may trigger a typical fire alarm system. In order to manage false alarms of conventional fire detection systems, a computer vision‐based fire detection algorithm is proposed in this paper. The proposed fire detection algorithm consists of two main parts: fire color modeling and motion detection. The algorithm can be used in parallel with conventional fire detection systems to reduce false alarms. It can also be deployed as a stand‐alone system to detect fire by using video frames acquired through a video acquisition device. A novel fire color model is developed in CIE L*a*b* color space to identify fire pixels. The proposed fire color model is tested with ten diverse video sequences including different types of fire. The experimental results are quite encouraging in terms of correctly classifying fire pixels according to color information only. The overall fire detection system's performance is tested over a benchmark fire video database, and its performance is compared with the state‐of‐the‐art fire detection method.     

An Iterative Processing Scheme for Enhancing the Map Reduce Using Map Information Storage in Wireless Environment

Wireless Personal Communications - The intention is to design the schemes for the enhancements for the enhancement of behaviour of map reduction scheme when it is employed for the iterative...     

一种自适应的雾天降质图像清晰化方法研究

用幂次变换函数取代传统的累积积分函数做直方图均衡,使输出图像亮度可调,显示更多细节。对Retinex理论求解法的Kimmel变分模型做了修改,增加了增强图像细节的因式项。将直方图幂次变换函数均衡化法和基于Retinex理论的图像增强法相结合,讨论了结合原则,提出了以图像方差指标作为结合与否的判据,达到了自适应处理薄、浓雾天降质图像的目的。实验表明,该方法既防止了单一进行直方图均衡在图像颜色细节上的畸变,又提高了基于Retinex理论图像增强法去浓雾的能力,取得了较好的视觉效果。     

对数字预失真的一种改进

为了弥补传统数字预失真方法在收敛速度和稳定性方面的不足,采用了一种根据输入信号功率的统计特性,将其分成不同等级的处理方法,并对提出的方法进行了分析和仿真。从仿真结果看,所提出的方法跟传统方法相比,将ACLR改善了7dB。     

An Efficient Method of Simulation for Time-Sharing Systems

Simulation of requests for service from a large number of low duty cycle independent users is apt to cause a severe computational load. A method is presented for the software implementation of an efficient simulator. It can be applied to the investigation of many time-sharing systems, such as satellite demand assignment (DA), computer time sharing, and traffic routing. More generally, the method generates independent multivariate Poisson distributions when the number of variables is very large and the value of the parameter in each distribution is very small.     

一种高效的门级电路可靠度估算方法

随着半导体技术的不断发展,芯片的集成度越来越高,软差错已经成为影响电路可靠性的关键因素之一。为了有效评估软差错对电路的影响,该文提出一种基于信号取值概率的门级电路可靠度估算方法。首先计算电路所有节点在软差错影响下的取值概率,然后用故障模拟分析电路整体可靠性。通过对基准电路的实验并与概率转移矩阵方法进行比较,该方法在不损失准确度的前提下,在时间与空间开销方面都具有优势,尤其适合估算特定向量和随机向量激励下电路的可靠度。     

一种有效的MIMO-OFDM系统时频同步方法

为了检测不同天线的时延和频偏,提高多输入多输出正交频分复用（MIMO-OFDM）系统同步算法性能,给出了一种有效的MIMO-OFDM系统定时和频率同步算法。该算法构造了一种新颖的基于恒包络零自相关码（CAZAC）的良好正交特性的训练序列结构,利用该训练序列结构可以有效地完成各发射天线的迟延和载波频偏估计。仿真结果表明,所给方法具有高的定时估计精度和低的计算复杂度,适用于各发射天线信号到达时延不同情况的MIMO-OFDM系统,具有很好的实用价值。     

一种适用于微弱信号盲提取的白化方法

独立分量分析(ICA)算法是解决盲信号分离(BSS)问题的最有效方法之一.ICA中,对观测信号预白化处理的作用至关重要.通常采用主分量分析(PCA)来进行预白化处理.实际中,在利用广播、电视等作为照射源的被动雷达系统中,观测信号通常被强噪声和干扰严重污染,这很大程度上降低了BSS方法的性能.然而,传统的BSS方法中没有...