A single-chip CMOS PCM codec with filters

A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.     

A single-chip CMOS filter/codec

A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.     

A single-chip I/SUP 2/L PCM codec

A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this signaling, the codec achieves a worst case idle channel noise of 13 dBrnC0.     

An integrated single-chip PCM voice codec with filters

A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.     

A single-channel PCM codec

A single channel PCM codec is described which is being manufactured for use in the new British Post Office range of digital PABXs. The codec works on the principle of converting to and from PCM using an intermediate delta sigma modulation code format. This technique allows relatively simple analog circuitry to be used in conjunction with a digital LSI chip to perform the conversion between the intermediate code and PCM. The codec meets all the relevant CCITT Recommendations with significant operating margins.     

Integrated PCM codec

Describes a one-chip PCM codec circuit which has been implemented in the CMOS process. The design uses two separate linear digital-to-analog converters, made with charge redistribution techniques. Experimental results show the circuit to meet accepted requirements and operate with very low power requirements.     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

A single-chip codec with switched-capacitor filters

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.     

A per-channel LSI codec for PCM communications

An LSI codec for voiceband signals is presented. A modified counting type encoding technique is employed to realize the codec, which uses coarse and fine reference current to discharge the integrating capacitor. The technique makes possible the realization of a high-speed counting-type codec for voice signals without imposing severe requirements on device parameters. This codec is composed of two LSI chips, i.e., a bipolar chip and an NMOS chip. An estimation sample of the LSI codec is fabricated and evaluated. Measured data of the codec performance are very close to the theoretically expected value. The performance assures that the device can be applied to channel banks, local switches, toll switches, and EPBXs.     

A PCM voice codec with on-chip filters

Describes a monolithic NMOS coder/decoder (codec) with associated CCD transversal minimum phase filters which has been successfully implemented. The codec operates by charge redistribution in a binary-weighted capacitor array, with a resistor chain to define individual steps. The experimental performance compares well with PCM codecs implemented with discrete components.     

A digital signal-processing codec filter for PCM applications

A programmable signal-processing codec filter (SICOFI) which performs its main filter functions by means of digital signal processing (DSP) is described. Besides PCM coding and band limitation, the circuit provides programmable adjustment of level control, impedance matching, hybrid balancing, and frequency response correction. Circuit performance, chip area, and power consumption have been optimized and a set of consistent CAD tools were developed for complete verification. Progress in circuit-design simulation techniques and an advanced CMOS technology allowed the economic integration of the analog and digital parts consisting of 36000 transistors on a 37.5-mm/SUP 2/ die.     

CMOS pulse-code-modulation voice codec

A standard CMOS technology has been employed in LSI realization of a pulse-code-modulation (PCM) encoder and decoder for per-channel applications in telephony. Innovations in the design of an operational amplifier, a comparator, and precision-ratioed capacitor arrays, all in standard CMOS, are reported.     

A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm² and dissipates 450 mW from a 3.3-V supply     

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.     

A self-calibrating single-chip CMOS camera with logarithmicresponse

A high-dynamic-range CMOS image sensor consisting of nonintegrating, continuously working photoreceptors with logarithmic response is presented. The nonuniformity problem caused by the device-to-device variations is greatly reduced by an implemented analog self-calibration. After performing this calibration, the remaining fixed pattern noise amounts to 3.8% (RMS) of an intensity decade at a uniform illumination of 1 W/m². The sensor provides a resolution of 384×288 pixels and a dynamic range of 6 decades in the intensity region from 3 mW/m² to 3 kW/m². It contains all components required for operating as a camera-on-a-chip. The image data can be read out either via a single analog line (video standard) or via a digital interface after undergoing an analog-to-digital conversion on the chip. Additional features like automatic exposure control, averaging of adjacent pixels, and digital zoom have been implemented, making the sensor suitable for a wide field of applications     

A dual-channel voice-band PCM codec using ΣΔ modulationtechnique

A dual-channel sigma-delta (ΣΔ) voice-band codec meeting AT&T/CCITT specifications is described. Its digital signal processing section has a bit-slice architecture which can be expanded to accommodate higher bit resolution. The active area per channel is 13 mm ² in a 1.5-μm CMOS process. It has only one power supply and the maximum power dissipation is 90 mW per channel. The crosstalk between channels is less than -71 dB     

PCM语音编解码系统中抗混叠滤波器的设计

PCM（脉冲编码调制）是一种编码方式,它可以将语音信号转换成数字信号。我们知道在音频系统中经常会出现信号混叠,基于这个原因,本文介绍了一种在PCM语音编解码系统所使用的抗混叠滤波。它是一个有源的、低通三阶巴特沃兹滤波器。     

A single-chip NMOS dual channel filter for PCM telephony applications

The implementation of a completely monolithic channel filter containing all frequency selective functions associated with a PCM line interface is described. The circuit utilizes switched capacitor techniques. Design of the overall architecture, the individual filter sections, and the operational amplifiers in NMOS technology is described. Experimental results are presented.