On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Dependence of channel electric field on device scaling

It has been shown previously that the maximum channel electric field Emin a MOSFET is the most important parameter relating to all hot-electron effects and that Emcan be represented as (V_{DS} - V_{DSAT})/l, wherelmay be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that Emhas a form of (V_{DS} - V_{DSAT})/ 0.22Tmin{ox}max{1/3}Xmin{j}max{1/2}. Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of Emagrees with Emdeduced from ISUBwithin about 5 percent; it can predict ISUB, which has been empirically correlated with hot-electron degradations.     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

Small-signal distributed FET model consistent with device scaling

A distributed modelling approach for micro- and millimetre-wave FETs is presented. Model identification is directly carried out on the bases of S-parameter measurements and electromagnetic analysis of the device layout without requiring cumbersome optimisation techniques. Experimental results confirm that the model is consistent with device scaling     

Technology and device scaling considerations for CMOS imagers

This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from “standard” CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while “standard” CMOS technologies may provide adequate imaging performance at the 2-1 μm generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 μm technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined     

Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate

We report the low-frequency noise characteristics of ultrathin body (UTB) p-channel MOSFETs with molybdenum (Mo) as the gate material. Using the number fluctuation model with correlated mobility fluctuation, the dependence of the noise behavior on bias condition is explained. The impact of nitrogen implantation (for gate work function engineering) on the noise behavior is also presented. An exponential increase in noise with nitrogen implant dose is attributed to interface-trap generation caused by nitrogen penetration through the gate oxide.     

The impact of device scaling on the current fluctuations inMOSFET's

The impact of device scaling on modern MOS technology is discussed in terms of the random telegraph signals and 1/f noise in MOSFET's. In addition to the more obvious effects of enhanced current fluctuations as the device is scaled down, we will show the influence of nonuniform distribution of threshold voltages along the channel in the context of device scaling. The role of fast interface states on the drain current fluctuations is also discussed. It will be shown that, compared to the oxide traps, fast interface states give rise to higher frequency RTS and 1/f noise, and that they become more important for devices operating in weak inversion     

CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.     

人体成分测量装置的设计

本文提出了一种能够测量人体总水、体脂、细胞内液、细胞外液含量的人体成分测量装置.采用生物电阻抗法,将人体分成理想的环段,使用8电极.电流电极将10kHz、50kHz、100kHz的安全电流引入人体,电压电极测量各个环段的电压进而得出其电阻抗,运用单片机运算出人体多种成分的含量.该装置以单片机为核心器件,具有操作简便、无损伤、快捷、安全和价廉的特点.     

Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is /spl sim/ 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Surface scaling analysis of hydrogels: From multiaffine to self-affine scaling

We show that smoothing of multiaffine surfaces that are generated by simulating a crosslinked polymer gel by a frustrated, triangular network of springs of random equilibrium lengths [G. M. Buendía, S. J. Mitchell, P. A. Rikvold, Phys. Rev. E, 66 (2002) 046119] changes the scaling behavior of the surfaces such that they become self-affine. The self-affine behavior is consistent with recent atomic force microscopy (AFM) studies of the surface structure of crosslinked polymer gels into which voids are introduced through templating by surfactant micelles [M. Chakrapani, S. J. Mitchell, D. H. Van Winkle, P. A. Rikvold, J. Colloid Interface Sci. 258 (2003) 186]. The smoothing process mimics the effect of the AFM tip that tends to flatten the soft gel surfaces. Both the experimental and the simulated surfaces have a non-trivial scaling behavior on small length scales, with a crossover to scale-independent behavior on large scales.     

The effects of device dimensions on the post-breakdown characteristics of ultrathin gate oxides

The effects of transistor channel length and width on post breakdown (BD) characteristics have been carefully investigated. As channel-length decreases, we have found that the probability of hard breakdown (HBD) increases and the soft breakdown (SBD) stability time decreases. However, these two quantities are found to be relatively insensitive to the channel width for long channel-length devices. Since SBD is unstable and finally causes the device failure, the so-called HBD prevalence ratio methodology has limitations which are particularly important in short-channel length devices. Our findings indicate that dimensional effects should be properly taken into account in the consideration of circuit reliability and for the application of any post-BD methodology.     

Power-generation potential of various IMPATT structures from a scaling approximation

The power potential of the double-drift and both complementary 1-sided silicon IMPATTS is estimated as a function of frequency, using a scaling approximation that accounts for the dependence of generation efficiency on bias-current density. The results show the n+?p junction IMPATT to be a superior choice for reliable power generation below 25 GHz, owing to its relatively low threshold-current density.     

Enhancement of charge storage performance in double-gate silicon nanocrystal memories with ultrathin body structure

We propose double-gate silicon nanocrystal memories (NCMs) with ultrathin body structure. Double-gate NCMs experimentally show larger threshold voltage shift (/spl Delta/V/sub th/) and longer charge retention time than single-gate NCMs. These superior behaviors in double-gate NCMs are explained by the increase in the body potential due to electrons in one side nanocrystals that prevent electrons in the other side nanocrystals from escaping. Thinner transistor body enhances the mutual influence between electrons in both sides. It is also found that the endurance characteristics are also improved by the reduced potential difference in the tunnel oxide.     

The impact of device scaling and power supply change on CMOS gateperformance

Based a new empirical mobility model that is solely dependent on V _gs, V_t, and T_ox and a corresponding saturation drain current (I_dsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T_ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V_dd (for low power applications) if V_t can be lowered     

Thermal stress and fracture in shear-constrained semiconductor device structures

The construction of semiconductor devices, as well as other electron devices, often requires the utilization of brittle materials, such as the semiconductor itself, as part of a larger structure. Thermal stress, caused by cooling from high temperature bonding operations, can cause fracture of the brittle part, due to thermal expansivity mismatch with other parts of the structure. This paper considers a widely used type of bond, consisting of a nonpenetrating butt-joint, wherein the parts develop thermal stresses by reason of shear constraint in a solder layer. This type of joint is therefore called a shear-constrained bond. A one-dimensional, elastic analytical model is presented, which predicts the location and orientation of the principal tensile stress in a shear-constrained brittle strip. The tensile stress required for brittle fracture is shown to be induced, primarily, by shear tractions in the solder layer which are applied to one face of the strip. Extended to a real structure, the model would predict the highest tensile stress at the outer periphery of a bond, and oriented at 45° with the plane of the bond interface. This prediction is found to be in agreement with the bulk of fracture experience in shear-constrained semiconductors.     

Drain-engineered hot-electron-resistant device structures: a review

Various MOS structures with specially designed drain regions are reviewed. Guidelines are established for the fabrication of hot-electron-resistant device structures. Additionally, suggestions are made with reference to device structures suitable for a manufacturing environment     

Nondestructive contactless electron-beam diagnostics of microelectronic device structures

An electron-beam diagnostic complex based on a scanning electron microscope is described. The complex allows the nondestructive contactless studies of microelectronic device structures and architectures and the simultaneous determination of the distribution of electrically active elements; i.e., the complex makes it possible to examine defects. The parallel diagnostic tests are based on the method of contactless detection of local electron-beam-induced potentials and on reflection electron microtomography in a scanning electron microscope.     

Modeling and characterization of CMOS-compatible high-voltage device structures

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.