A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

On configurable oversampled A/D converters

An oversampled A/D (analog-to-digital) converter that can be configured as either a sigma-delta converter or an incremental converter is presented. This is an oversampled instrumentation converter that cancels offset and 1/f noise. The converter architecture is based on a mixed analog-digital integrator (MADI) concept. This concept is shown to lead to a very simple and modular architecture. The implemented converter also allows selection of the converter order and the decimation factor in order to find the best tradeoff between resolution, conversion time or bandwidth, and power consumption. As the converter architecture is completely modular, it can rapidly be tailored for a specific application with minimized silicon area. The circuit achieves a resolution of 16 b on a range of ±650 mV and compensates the offset and the even-order harmonics to a nonobservable level     

A 15-b pipelined CMOS floating-point A/D converter

A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW     

A low-power BiCMOS switched-capacitor filter for audio codecapplications

A fully integrated fourth-order filter embedded in a complete 16-b oversampled D/A converter to be used in an audio stereo codec is presented. The possible noise and distortion sources have been accurately evaluated in the design and their contributions have been properly limited. This allows the reduction of the power consumption while satisfying the application requirements. The filter is realized in 0.7-μm BiCMOS technology with an active area of about 1.3 mm² . A total harmonic distortion (THD) of -75 dB for a full scale input signal and an SNR of 96 dB have been achieved. The power consumption of the filter has been maintained within about 40 mW from a single 5-V supply voltage     

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributedtrack-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm² in 0.5-μm standard digital CMOS technology     

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converterin a 0.25-μm digital CMOS process

The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 μm CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm² and consumes less than 187 mW of power     

A CMOS ratio-independent and gain-insensitive algorithmicanalog-to-digital converter

This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 μm double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion     

Area-efficient multichannel oversampled PCM voice-band coder

The authors describe the design of a four-channel oversampled A/D (analog/digital) converter with transmit filter for voice-band application. The decimator filter is timeshared between the four channels and the architecture of the sigma-delta coder is selected on the basis of minimizing the chip area. The analog front-end loop is fully differential to minimize the channel-to-channel crosstalk. The key issues in designing a multichannel oversampled A/D converter for area efficiency are addressed. It is concluded that for the multichannel telephony voice-band application implemented in CMOS technology, a first-order loop is most area-efficient. The performance of the coder has been evaluated and it is shown to have a dynamic range of 79 dB, to occupy a total active area of 33000 mils² or 8250 mils² per channel, and to meet the D3 specifications for the transmit filter. It runs on a 5-V supply and consumes 50 mW per channel     

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effective sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping circuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5-μm CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm² dissipating 550 μW while the digital-to-analog converter occupies 0.28 mm² dissipating 600 μW     

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs(most-significant-bits)-plus-5 LSBs(least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach,with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method,an 8-channel 10-bit 200-kS/s SAR ADC(successive-approximation -register analog-to-digital converter) IP core for a touch screen SoC(system-on-chip) is implemented in a 0.18μm 1P5M CMOS logic process.Design considerations for the touch sc...     

A 12-b 5-Msample/s two-step CMOS A/D converter

Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1-μm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm × 3.7 mm     

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converter's design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.     

A novel time-based low-power pipeline analog to digital converter

A new power reduction technique for analog-to-digital converters is proposed in this paper. A novel current-mode algorithm which uses time to perform analog-to-digital conversion has been described and a 12 bit 100-ksample/s time-based pipeline analog to digital converter has been designed and simulated in standard 90-nm CMOS technology based on introduced structure. Employed circuit techniques include a continues-time comparator, bottom plate sampling, digital correction and a state machine. A time based-mechanism has been used for subtraction and amplification. Simulation results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio of 69.8 dB, a peak spurious-free dynamic range of 75 dB, a total harmonic distortion of 73 dB, and a peak integral nonlinearity of 0.85 least significant bits. The total power dissipation is 90 μW from a 3-V supply.     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

A monolithic 2-b delta-sigma A/D converter

A monolithic 20-b analog-to-digital (A/D) converter using oversampling techniques which is implemented in standard 3-μm CMOS technology is described. The integrated circuit contains a fourth-order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The modulator consists of a continuous-time chopper-stabilized front end, and a switched-capacitor loop filter and comparator. The dynamic range is 123 dB over a DC-to-500-Hz bandwidth, and the signal-to-noise-harmonic-distortion ratio is 126 dB. The chip consumes 125 mW power and has an area of 29.25 mm²     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

A 13.5-b 1.2-V micropower extended counting A/D converter

This work presents a study of the extended counting technique for a 1.2-V micropower voice-band A/D converter. This extended counting technique is a blend of ΣΔ modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a first-order ΣΔ modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8-μm CMOS. With a 1.2-V power supply, it consumes 150 μW of power at a 16-kHz Nyquist sampling frequency. The measured peak S/(N+THD) was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about 1.3×1 mm² of chip area. This is considerably less than a complete ΣΔ modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area