Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

Comment on 'biased model reduction by simplified Routh approximation method'

For the original article see ibid., vol.23, p.1045-7 (1987). Sastry and Krishnamurthy recently suggested a 'simplified' Routh approximation method (SRAM) for model order reduction of linear systems. They claim that one of the major advantages of the technique over the much used Routh approximation method is having only to use the so-called alpha -parameters to obtain the reduced model instead of both the alpha - and beta -parameters. They also claim that the models produced by this simplified approach exhibit the desirable properties of the Routh method, i.e. stability preservation and time moment/Markov parameter retention. While the latter claim cannot be doubted, the former is based on experimental evidence only, and not proved mathematically; consequently it must be viewed with suspicion. The commenter shows that stability is not preserved in general when using this simplified approach to obtain reduced model of orders higher than 4. It is suggested that great care be applied, if this method is used to check the stability of the reduced models.<>     

Compact Code Generation for Tightly-Coupled Processor Arrays

In this paper, we consider programmable tightly-coupled processor arrays consisting of interconnected small light-weight VLIW cores, which can exploit both loop-level parallelism and instruction-level parallelism. These arrays are well suited for compute-intensive nested loop applications often providing a higher power and area efficiency compared with commercial off-the-shelf processors. They are ideal candidates for accelerating the computation of nested loop programs in future heterogeneous systems, where energy efficiency is one of the most important design goals for overall system-on-chip design. In this context, we present a novel design methodology for the mapping of nested loop programs onto such processor arrays. Key features of our approach are: (1) Design entry in form of a functional programming language and loop parallelization in the polyhedron model, (2) support of zero-overhead looping not only for innermost loops but also for arbitrarily nested loops. Processors of such arrays are often limited in instruction memory size to reduce the area and power consumption. Hence, (3) we present methods for code compaction and code generation, and integrated these methods into a design tool. Finally, (4) we evaluated selected benchmarks by comparing our code generator with the Trimaran and VEX compiler frameworks. As the results show, our approach can reduce the size of the generated processor codes up to 64 % (Trimaran) and 55 % (VEX) while at the same time achieving a significant higher throughput.     

The distributed voting strategy for fault diagnosis and reconfiguration of linear processor arrays

A new strategy for fault diagnosis and reconfiguration of linear processor arrays is proposed. This strategy can be implemented in a distributed manner, suitable for arrays with a large number of processors such as those implemented by VLSI and WSI techniques. The proposed fault diagnosis is based on the distributed voting technique. Additional links are added for fault diagnosis. These links are also used, when there is a processor failure, for communication between the processors. Some reconfiguration schemes are also presented emphasizing the distributed approach.     

Redundancy effect on yield of binary tree RAMs

Recently, a radically new RAM architecture was proposed by Jarwala and Pradhan [10] called TRAM architecture. A 64M version of this architecture is being prototyped by a DRAM manufacturer in Japan. The yield sensitivity of this binary Tree Dynamic RAMs (TRAMs) at variations in tree-depth and redundancy level is investigated in this article. It is analyzed not only the yield of all good chips, but also the probability of generating partially good chips. To this purpose a new stochastic yield model, overcoming the drawbacks of the existing ones, is used. The model is a straightforward one and easy to use in parametric studies of chip's yield versus redundancy level and reconfiguration strategies.     

Control generation in the design of processor arrays

The problem of mapping algorithms onto regular arrays has received great attention in the past. Results are available on the mapping of regular algorithms onto systolic or wavefront arrays. On the other hand, many algorithms that can be implemented on parallel architectures are not completely regular but are composed of a set of regular subalgorithms. Recently, a class of configurable processor arrays has been proposed that allows the efficient implementation of piecewise regular algorithms. In contrary to pure systolic of wavefront arrays they are distinguished by a dynamic configuration structure. The known trajectories, however, cannot be applied to the design of configurable processor arrays because the functions of the procesing elements and the interconnection structure are time- and space-dependent. In this paper, a systematic procedure is introduced that allows the efficient design of configurable processor arrays including the specification of the processing elements and the generation of control signals. Control signals are propagated through the processor array. The proposed design trajectory can be used for the design of regular arrays or configurable arrays.     

宽频带2D相控阵声束特性及脉冲场分析

二维（2D）换能阵列在横向和侧向两个方向上可实现超声波束的聚焦控制,在整个三维空间实现聚焦声束的扫描。文章通过对波束采用系统理论仿真的方法,确定优化适于医学成象的参数。研究了宽带2D阵列波束的频率特性,并对阵列阵元尺寸和阵元数对波束特性的影响效果进行了研究。最后讨论了在整个换能器孔径上阵元随机分布的一些稀疏阵列的波束特性。     

Probability of correctness of processor-array outputs usingperiodic concurrent error detection

Processor arrays, featuring modularity, regular interconnection, and high parallelism, are well suited for VLSI/WSI implementation and specific applications with high computational requirements. Error detection and recovery are important for some applications of processor arrays. Concurrent error detection (CED) techniques, which check normal system operations, are designed to detect errors caused by transient and intermittent faults, However, CED techniques typically suffer from costly hardware penalties or performance costs. This paper describes the periodic application of concurrent error detection (PACED) technique which allows the performance costs incurred through the use of time-redundant CED in processor array architectures to be reduced. The application of CED is varied in both time and space to provide probabilistic detection of errors in processor arrays. The probability of correctness of outputs from processor arrays is studied. Formulae are derived that predict, upon error detection, the amount of possibly erroneous output, for single processors, linear arrays and 2-dimensional mesh processor arrays. The results indicate that the error coverage can be surprisingly high when PACED is applied in processor arrays, e.g., 95% for checking performed 50% of the time     

Gossip-Based Load Balance Strategy in Big Data Systems with Hierarchical Processors

In big data systems, data are assigned to different processors by the system manager, which has a large amount of work to perform, such as achieving load balances and allocating data to the system processors in a centralized way. To alleviate its load, we claim that load balancing can be conducted in a decentralized way, and thus, the system manager need not be in charge of this task anymore. Two decentralized approaches are proposed for load balancing schemes, namely, a utilization scheme based on a load balance algorithm (UBLB) and a number of layers scheme based on a load balance algorithm (NLBLB). In the UBLB scheme, considering the hierarchy of the processor’s processing abilities, a gossip-based algorithm is proposed to achieve load balance using the jobs’ utilizations as load balance indicators in addition to the number of jobs. The reason for this action is that the processor’s process abilities are different from one another. Thus, the utilization indicator is more reasonable. In the NLBLB scheme, the processors are classified into different layers according to their processing abilities. In each layer, a sub-load balance is conducted, which means that the UBLB is achieved in a sub-region. The efficiencies of the two proposed schemes are validated by simulation, which proves their positive effect.     

A dynamically reconfigurable interconnect for array processors

Reconfigurability of processor arrays is important due to two reasons (1) to efficiently execute different algorithms and (2) to isolate faulty processors. An array processor that is reconfigurable by the user any number of times to yield a different topology or to isolate faults is envisaged in this paper. The system has a host or controller that broadcasts a command to the interconnect to configure itself into a particular fashion. The interconnect uses static-RAM programming technology and can be programmed to different configurations by sending a different set of bits to the configuration random access memory (RAM) in the interconnect. We present three designs reconfigurable into array, ring, mesh, or Illiac mesh topologies. The first design provides no redundancy or fault tolerance. The second design is capable of graceful degradation by bypassing faulty elements. The third design is capable of graceful degradation by rerouting. The details of the interconnect and the configuration RAM contents for typical configurations are illustrated. It is seen that reconfigurable interconnect results in a highly reconfigurable or polymorphic computer     

A Model-Based Processor Design for Smart Microsensor Arrays [Applications Corner]

In this article, we discuss the design of a smart-physics-based processor for microcantilever sensor arrays. The processor is coupled to a microelectromechanical sensor and estimates the presence of critical materials or chemicals in solution. We first briefly present microcantilever sensors and then discuss the microcantilever sensor array design, which consists of the cantilever physics propagation model, cantilever array measurement model, model-based parameter estimator design, and model-based processor (MBP) design. Finally, we end with experimental results and conclusions     

Design and characterization of analog VLSI neural network modules

A systematic method for testing large arrays of analog, digital, or mixed-signal circuit components that constitute VLSI neural networks is described. This detailed testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2 μm double-polysilicon CMOS technologies are presented to demonstrate the testing procedure     

Parallel asynchronous focal plane array processing

A new approach to focal plane processing based on silicon injection mode devices is suggested. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind the focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. No multiplexing, digitization or serial processing would occur in the preprocessing stage. High performance is expected because approximately linear pulse coding has already been observed for input currents ranging over six orders of magnitude down to one picoampere with noise referred to input of about 10 femtoamperes. Very low power requirements suggest utility in space and in conjunction with very large arrays. Multispectral processing is possible because of compatibility with the cryogenic environment of high performance infrared detectors.     

A study of space-tapered arrays

Previous works on nonuniformly spaced arrays are first critically reviewed, then an exhaustive study of a few small arrays is made. The results reveal that among a large number of possible element arrangements, only very few yield reasonably low sidelobe level. Although the majority of these few arrays are characterized by space-tapering, an overwhelming number of space-tapered arrays do not have low sidelobe level. Some statistical studies are made in order to relate the sidelobe level to the element arrangement. Finally, in the light of rather complete information of these arrays, a comparative study is made on some designs which are proposed by a few authors. The results show that none of them are truly optimum.     

New 2D systolic array algorithm for DCT/DST

Presents an algorithm and the architecture of a 2D systolic array processor for the DCT (discrete cosine transform) and the DST (discrete sine transform). It is based on the IDFT (inverse discrete Fourier transform) version of the Goertzel algorithm via Horner's rule. This 2D systolic array for the DCT/DST can be met by achieving a systematic technique for transforming algorithms to specific forms for mapping onto 2D systolic arrays.<>     

激光测距中APD阵列探测信噪比分析

APD阵列可提高光子探测效率,然而在回波探测概率提高的同时提高噪声探测概率,因此需合理选择阵列单元数以提高探测信噪比。根据回波和噪声在距离门内的分布情况,结合光子探测概率,建立了盖革模式下APD阵列探测信噪比随阵列单元数的变化模型。讨论了回波光子数、背景噪声强度、回波在门控内位置、占空比等因素对探测信噪比的影响。分析结果表明,提高回波光子数、探测器占空比、轨道预报精度有助于增加APD阵列的探测信噪比;4元APD阵列适用于回波光子数小于0.1、门控内噪声光子数小于1的观测情况,而回波和噪声强度较强时,25元APD阵列能够取得相对较优的探测信噪比。建立的APD阵列探测信噪比模型有助于快速选择APD阵列单元数以达到较高探测信噪比。     

Vertical 3D Printed Forest-Inspired Hierarchical Plasmonic Superstructure for Photocatalysis

Efficient light-harvesting is of significant importance to achieve high solar energy utilization efficiency for various solar-driven technologies. Compared with a 2D planar structure, a 3D plasmonic structure can largely increase the light adsorption/interaction areas and also utilizes the plasmonic effect to achieve much higher light utilization efficiency. However, this remains challenging in terms of structural design, reliable manufacturing, and ability to scale up. Herein, inspired by the light absorption strategy of natural forests, a hierarchical plasmonic superstructure is demonstrated composed of vertical TiO₂ pillar arrays (as tree trunks), dense nanorod arrays (as branches), and a large number of plasmonic Au nanoparticles (as leaves). Such a forest-like plasmonic superstructure can effectively absorb light from the surface plasmonic resonance effects of Au nanoparticles and the multiple scattering of light in the hierarchical branched structure. The strong light absorption and abundant photocatalytic active sites help yield a 15-fold higher nitrogen photo-fixation activity than that of the flat TiO₂ films decorated with Au nanoparticles. The study provides an effective strategy to construct 3D plasmonic superstructures with excellent light-harvesting efficiency and high stability and can be readily applied to a range of light-driven applications     

High-end server system partitioning for cost reduction

In this paper, we demonstrate the use of finite-dimension linear programming to maximize the number of partial good multicore processor chips in a symmetric multiprocessing (SMP) node of a given logical size and physical footprint. It is asserted that to the first order the cost of a productized processor chip will be proportional to the scrap of a processor chip containing good cores but being unusable for the implementation of an SMP node. Therefore, the tradeoff between the number of processing units (PUs) on a chip and the total number of PUs on an SMP node is examined. This paper shows that an optimized SMP offering can be found so that the total chip cost of a high-end system can be minimized. However, such cost reduction will limit the SMP node size for a given processor chip yield. It will also be shown that as the chip yield improves the SMP node size that can be profitably implemented will increase.     

Performance of wireless CDMA with M-ary orthogonal modulation andcell site antenna arrays

An antenna array-based base station receiver structure for wireless direct-sequence code-division multiple-access (DS/CDMA) with M-ary orthogonal modulation is proposed. The base station uses an antenna array beamformer-RAKE structure with noncoherent equal gain combining. The receiver consists of a “front end” beamsteering processor feeding a conventional noncoherent RAKE combiner. The performance of the proposed receiver with closed loop power control in multipath fading channels is evaluated. Expressions for the system uncoded bit-error probability (BEP) as a function of the number of users, number of antennas, and the angle spread are derived for different power control scenarios. The system capacity in terms of number of users that can be supported for a given uncoded BEP is also evaluated. Analysis results show a performance improvement in terms of the system capacity due to the use of antenna arrays and the associated signal processing at the base station. In particular, analysis results show an increase in system capacity that is proportional to the number of antennas. They also show an additional performance improvement due to space diversity gain provided by the array for nonzero angle spreads