Minimizing detection-to-boosting latency toward low-power error-resilient circuits

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.     

Memristor-based combinational circuits: A design methodology for encoders/decoders

The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2ⁿ×n (n×2ⁿ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.     

Shifter circuits for {2n+1, 2n, 2n−1} RNS

Shifter circuits are introduced for residue number systems (RNS) with bases composed of the moduli set Shifter circuits for {2n+1, 2n, 2n−1} RNS . The proposed circuits are straightforward to design and their implementation has very small area and delay, making shift operations in RNS inexpensive.     

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP.     

Placement algorithm for the optimal synthesized design of CMOS logic cells

A systematic placement algorithm is described for the design of CMOS logic cells. Unlike the other placement algorithms that apply only to NAND/NOR circuits or that are very time consuming, the proposed algorithm applies to any kind of CMOS circuit, and has no restriction as to the NAND/NOR circuits. Furthercmore, it applies to both planar and non-planar circuits. In addition, since a very efficient graph-theoretic approach is used as a constructive algorithm which generates a near optimal initial placement combined with an iterative approach by simulated annealing, an optimum result can be obtained in less time. The layout style of a transistor chain is used which, in conjunction with the optimal synthesized design approach using switching network logic, constitutes a systematic method for the design automation of high-speed VLSI circuits.     

一种宽带OFDM信号接收电路的设计与实现

针对无线局域网(WLAN)系统中的宽带OFDM信号接收,提出了一种OFDM信号接收电路设计。设计的接收电路主要包括正交下变频电路和全直流耦合驱动电路两个部分,电路采用差分结构,能够有效抑制直流漂移和偶次谐波,满足对宽带OFDM信号的正交下变频接收、采样要求。其中提出的宽带信号全直流耦合驱动电路设计方法,可应用于其他宽带信号的采样驱动,特别是在高速采样驱动电路设计中,适应信号带宽可达到DC～1 GHz。通过实际测试结果,验证了设计方法的正确性和工程实用性。     

A Simple Method for Millimeter-Wave Finline Balanced Mixer Design Using Three-Dimensional Field Simulation Software

In this paper, a simple method for millimeter-wave finline balanced mixer design using three-dimensional field simulation software has been proposed. The method can be widely used to design the diode-based circuits, especially for the circuit structures with orthogonal field in some specific hybrid integrated circuits which are unavailable to be designed using the circuit simulator. In these circuits, the power directly at diodes is correlated to the input reflection coefficient. The diodes mounted on the finline circuits are defined as impedance boundary in the commercial computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS) model, and hence simulation with the use of HFSS can be implemented to optimize the input matching network of the finline circuits for transferring maximum power to the diodes. Two finline balanced mixers at U-band using commercial GaAs Schottky diodes have been designed and fabricated to validate this method. Matching structures at the radio frequency (RF) port have been employed for a better return loss and a lower conversion loss. Experiment results are presented and show good agreement with simulation data. The proposed method has proven to be useful for the design of millimeter-wave mixers in finline technique.     

抗干扰导航接收机射频前端线性度优化设计

针对干扰条件下无自动增益控制(AGC)电路的卫星导航接收机射频前端的设计,在给定A/D采样芯片和混频器的条件下,根据抗干扰需求,提出了线性度指标的优化设计方法,得出了各级电路的增益、1dB压缩点、三阶交调截点和噪声系数的求解方法,以此指导器件选型。根据此优化设计方法,设计了某卫星导航系统的一种接收机射频前端,达到预期抗干扰效果,证明此方法有效可行。     

A Fully-Balanced Operational Amplifier

A method for analysis and design of Fully-Differential (F-D) analog circuits is presented. It is based on defining a Fully-Balanced Operational Amplifier (FBOA), which works with balanced signals; this is with common mode and differential mode voltages as a whole, allowing analysis and design of both operational modes behaviors. The FBOA can be implemented as a monolithic circuit but it can also be easily built using standard single-ended (S-E) operational amplifiers. This structure can be found in many typical F-D feedback circuits, providing a new framework for their analysis. The proposed device also provides a simple way to design F-D circuits and allows the implementation of inverter and non-inverter F-D topologies. Typical application circuits are analyzed and, as a design example, a "double-mode oscillator (a circuit that has independent common mode and differential mode oscillations) is presented. Experimental tests performed on this circuit validate the proposed technique.     

基于DNA域编码的余三码四位减法器的设计

DNA分子逻辑电路的设计是DNA计算领域的重要研究方向。该文针对当前双轨分子逻辑电路复杂度高、响应时间慢的问题,提出一种基于域编码策略的DNA逻辑电路设计的新方法。该文设计了“多输入1输出”逻辑运算模块,构建了扇出门和放大器,并利用所构建的电路模块搭建了4位平方根分子逻辑电路,与经典的双轨策略下的4位平方根电路相比,反应物的数量由双轨的130种降低为61种,系统响应时间缩减为双轨的1/24,大大简化了电路的复杂度,提高了系统的响应速度,进一步验证了域编码策略在分子逻辑电路设计中的有效性。为了深度解析基于域编码策略的大规模复杂分子逻辑电路的设计思想,该文构造了“余三码四位减法器”,为设计大规模功能性DNA逻辑电路提供了更多的解决方案。     

Adder design using 5-input majority gate in a novel “Multilayer Gate Design Paradigm” for Quantum Dot Cellular Automata Circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an xor gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a$2^7!-!1$sequence length. The circuits were fabricated in a SiGe BiCMOS technology with$f _T = 120~hboxGHz$. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.     

A Comprehensive Delay Model for CMOS CML Circuits

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-$mu{hbox {m}}$ CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.      

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology

A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3Vinterface.Anew level converter realized with +1.8Vdevices that can convert 0/1Vvoltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.     

Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs     

A current-/voltage-controlled four-slope operation square-/triangular-wave generator and a dual-mode pulse width modulation signal generator employing current-feedback operational amplifiers

This paper presents a current-feedback operational amplifier (CFOA)-based current-/voltage-controlled four-slope operation square-/triangular-wave generator. The proposed circuit can adjust the duty cycle of the output waveforms in a current- or voltage-controlled manner, and an external resistor is used to independently control its oscillation frequency. In addition, the DC level of the triangular wave can be adjusted by tuning an input voltage source. This paper also presents a CFOA-based dual-mode pulse width modulation (PWM) signal generator derived from the proposed square-/triangular-wave generator. The literature review in this paper includes previous designs, circuit operations, and the non-ideal effects and design considerations of the proposed circuits. Prototype circuits built with commercially available CFOA integrated circuits (ICs) (AD844ANs) and discrete passive components were used to execute experimental tests to verify the feasibility of the proposed circuits. The experimental results of this study are in agreement with the theoretical analysis.