共查询到19条相似文献,搜索用时 171 毫秒
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理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明:边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流. 相似文献
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文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。 相似文献
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在Si(110)衬底上制备了Ge源n型Si沟道隧穿场效应晶体管(TFET)。本文研究了温度对Ge源Si TFET器件的电学性能的影响。温度相关性研究显示器件漏电流主要由漏区的Shockley - Read - Hall (SRH) 产生于复合电流决定。器件开态电流随温度升高而增加,这是因为温度升高材料禁带宽度减小,隧穿几率增大。界面缺陷引起的隧穿电流的亚阈值摆幅随温度升高而变差,但是带间隧穿电流的亚阈值摆幅不随温度变化而变化。 相似文献
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双极场引晶体管:Ⅲ.短沟道电化电流理论(双MOS栅纯基) 总被引:1,自引:1,他引:0
本文描述双极场引晶体管(BiFET)短沟道理论.晶体管分成两个区域,源区和漏区.每区在特定外加端电压下既可为电子或空穴发射区又可为电子或空穴收集区.把两维无缺陷Shockley方程分离为两个以表面势为参变量的一维方程,并运用源区和漏区界面处电子电流和空穴电流连续性,得到在源区和漏区内解析方程.典型BiFET包括薄纯基上两个等同金属氧化物硅(MOS)栅.用图形提供实用硅基和氧化层厚度范围内,随直流电压变化,输出和转移电流和电导总量,电子沟道与空穴沟道分量,和两区电学长度.报道前没考虑沟道缩短的偏差. 相似文献
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本文描述双极场引晶体管(BiFET)短沟道理论.晶体管分成两个区域,源区和漏区.每区在特定外加端电压下既可为电子或空穴发射区又可为电子或空穴收集区.把两维无缺陷Shockley方程分离为两个以表面势为参变量的一维方程,并运用源区和漏区界面处电子电流和空穴电流连续性,得到在源区和漏区内解析方程.典型BiFET包括薄纯基上两个等同金属氧化物硅(MOS)栅.用图形提供实用硅基和氧化层厚度范围内,随直流电压变化,输出和转移电流和电导总量,电子沟道与空穴沟道分量,和两区电学长度.报道前没考虑沟道缩短的偏差. 相似文献
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本文描述双极场引晶体管(BiFET)短沟道解析理论,用解析理论分别计算飘移扩散电流.上月文章用单项电化电流描述飘移扩散电流.正如那篇文章里,两维晶体管分成两个区域,源区和漏区.每区在特定外加端电压下既可为电子或空穴发射区又可为电子或空穴收集区.把两维无缺陷Shockley方程分离为两个以表面势为参变量的一维方程,并运用源区和漏区界面处电子电流和空穴电流连续性,得到在源区和漏区内解析方程.典型BiFET包括薄纯基上两个等同金属氧化物硅(MOS)栅.用图形提供实用硅基和氧化层厚度范围内,随直流电压变化,输出和转移电流和电导总量,电子沟道与空穴沟道飘移扩散分量,和两区电学长度.描述两区短沟道理论相对一区长沟道理论偏差. 相似文献
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《Electron Device Letters, IEEE》2008,29(11):1249-1251
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深入研究了亚30nm CMOS关键工艺技术,特别是提出了一种新的低成本的提高空穴迁移率的技术--Ge预非晶化S/D延伸区诱生沟道应变技术,它使栅长90nm pMOS空穴有效迁移率在0.6MV/cm电场下提高32%. 而且空穴有效迁移率的改善,随器件特征尺寸缩小而增强. 利用零阶劳厄线衍射的大角度会聚束电子衍射分析表明,在沟道区相应的压应变为-3.6%. 在集成技术优化的基础上,研制成功了高性能栅长22nm应变沟道CMOS器件及栅长27nm CMOS 32分频器电路(其中分别嵌入了57级/201级环形振荡器), EOT为1.2nm,具有Ni自对准硅化物. 相似文献
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In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device. 相似文献
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Mike Schwarz Thomas Holtij Alexander KloesBenjamín Iñíguez 《Solid-state electronics》2011,63(1):119-129
In this paper we present a new approach to calculate the channel electric field within a Schottky barrier Double-Gate MOSFET (SB-DG-MOSFET) in subthreshold region by solving Poissons equation. The Poisson equation is solved two dimensionally in an analytical closed-form with the conformal mapping technique. A comparison with data simulated by TCAD Sentaurus simulator for channel lengths down to 22 nm was made and shows an accurate agreement. Futhermore, a new way for the estimation of the tunneling current in SB-DG-MOSFET by applying the above 2D solution for the electric field and a 2D solution of the electrostatic potential is presented. Calculating the tunneling current, we use Wentzel-Kramers-Brillouin (WKB) approximation for the estimation of the tunneling probability. For the calculation of the tunneling and thermionic current a comparison with TCAD Sentaurus for channel lengths down to 65 nm was made. 相似文献
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Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs 总被引:2,自引:0,他引:2
Qiuxia Xu Xiaofeng Duan Haihua Liu Zhengsheng Han Tianchun Ye 《Electron Devices, IEEE Transactions on》2007,54(6):1394-1401
Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed. 相似文献
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King-Jien Chui Kah-Wee Ang Narayanan Balasubramanian Ming-Fu Li Ganesh S. Samudra Yee-Chia Yeo 《Electron Devices, IEEE Transactions on》2007,54(2):249-256
A novel strained-silicon (Si) n-MOSFET with 50-nm gate length is reported. The strained n-MOSFET features silicon-carbon (Si1-yCy) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of Si1-yCy in the S/D regions. The carbon mole fraction incorporated is 0.013. Lattice mismatch of ~0.56% between Si 0.987C0.013 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron-mobility enhancement. The conduction-band offset DeltaEc between the Si0.987 C0.013 source and the strained Si channel could also contribute to an increased electron injection velocity nuinj from the source. Implementation of the Si0.987 C0.013 S/D regions for n-MOSFET provides significant drive current IDsat enhancement of up to 50% at a gate length of 50 nm 相似文献
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Sub-10-nm bulk n-MOSFET(metal-oxide-semiconductor field effect transistor) direct source-todrain tunneling current density using Wentzel-Krammers-Brillouin(WKB) transmission tunneling theory has been simulated.The dependence of the source-to-drain tunneling current on channel length and barrier height is examined.Inversion layer quantization,band-gap narrowing,and drain induced barrier lowering effects have been included in the model.It has been observed that the leakage current density increases severely below 4 nm channel lengths,thus putting a limit to the scaling down of the MOSFETs.The results match closely with the numerical results already reported in literatures. 相似文献
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Shiying Xiong Bokor J. Qi Xiang Fisher P. Dudley I. Paula Rao Haihong Wang En B. 《Semiconductor Manufacturing, IEEE Transactions on》2004,17(3):357-361
An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I/sub OFF/ increase (for 40 nm gate length) in the I/sub OFF/-I/sub ON/ plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I/sub OFF/-I/sub ON/ curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (EdgeRMS<2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length. 相似文献
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基于有限元方法对一款具有SiGe源/漏结构的纳米PMOSEFT进行了建模与分析,沟道应变的计算结果与CBED实验测量值呈现良好的一致性,最小误差仅为1.02×10-4.对新型的SiC源/漏结构的纳米NMOSFET的类似研究表明,栅长越短,应变对沟道的影响越显著.另一方面,采用TCAD工具Sentaurus通过工艺级仿真... 相似文献