A numerical analysis of avalanche breakdown in short-channel MOSFETs

Recently, the electrical characteristics for the short channel MOSFETs (Metal-Oxide-Semiconductor field effect transistor) have become important because of the increasing density of LSIs (Large Scale Integrated Circuits). One of the methods to understand the characteristics of the short channel MOSFETs is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the two-dimensional method. In this paper, the drain breakdown characteristics for the short channel MOSFETs are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.     

Analysis of the drain breakdown mechanism in ultra-thin-film SOIMOSFETs

The drain breakdown phenomenon in ultra-thin-film (silicon-on-insulator) SOI MOSFETs has been studied. Two-dimensional simulation revealed that the thinning of the SOI film brings about an increase in the drain electric field due to the two-dimensional effect, causing a significant lowering in the drain breakdown voltage, as has been commonly seen in ultra-thin-film SOI MOSFETs. The simulation also showed that the lowered drain breakdown voltage recovered almost to its original value when the drain SOI thickness was restored, suggesting that the drain structure, rather than the source, plays a major role in determining the drain breakdown voltage. Experiments using an asymmetric device structure supported this hypothesis, showing that the breakdown voltage was mostly dependent on the drain structure, the initial potential barrier height at the source-SOI-body junction being only a minor factor. Transient simulation was also carried out to investigate the detailed breakdown process, showing that holes accumulate near the source-SOI-body junction at a high drain bias, eventually forward-biasing the junction. These results indicate that a careful drain design and/or proper choice of the SOI thickness as well as the supply voltage are quite important for realizing high performance of ultra-thin-film SOI MOSFETs     

Investigation of the proportional difference characteristics of MOSFETs

A proportional difference operator method has been presented to study the electrical characteristics of MOSFETs in all the operating regimes. It is shown that the proportional difference drain current versus the drain voltage exhibits a spectrum feature in all regions of operation including the subthreshold regime and the saturation regime. The amplitude of the spectrum peak is related to the effective carrier mobility, and the spectrum peak position responds to the voltage constants in each operating region (including the subthreshold and saturation regime) of a MOSFET. This then enables the more important statistic performance of MOSFETs to be evaluated using the proportional difference operator method. Analytical expressions for computing these parameters (such as effective carrier mobility, thermal voltage, threshold voltage etc.) have been derived and experimental results have been presented.     

Threshold voltage of small-geometry Si MOSFETs

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

一种测试功率MOSFET热阻的新方法

阐述了一种测试功率MOSFET热阻的新方法。该方法选取漏源电流作为温度敏感参数,在相同漏源电压和栅源电压幅度下,当栅源电压条件由直流形式变为脉冲形式时,漏源电流是有差异的,这一差异是由结温的不同造成的。而脉冲栅源电压下环境温度的调整可以用来模拟直流条件下的结温,由此可以测得器件在直流条件下的热阻。该方法具有精度高、实现容易和操作方便等优点,可作为功率MOS器件结温和热阻的有效测试方法。     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

A method to extract mobility degradation and total seriesresistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed     

Excellent immunity of GIDL to hot-electron stress in reoxidizednitrided gate oxide MOSFET's

The authors present an investigation of the enhancement in gate-induced drain leakage (GIDL) caused by hot-electron stress in MOSFETs with control oxides, nitrided oxides, and reoxidized nitrided oxides as gate dielectrics. The contributions of interface state generation and electron trapping to GIDL enhancement in these MOSFETs were compared based on stress condition and stress time dependencies. Although no improvement resulted at large drain biases, under low drain voltage conditions, reoxidized nitrided oxides exhibited less GIDL enhancement under hot-electron stress than a nitrided oxide that was not reoxidized     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

全电流模型的比例差分特性

用比例差分算符 (PDO)方法研究了长沟 MOSFET在各个工作区域 (亚阈区和饱和区 )的比例差分特性 .利用 PDO方法研究全电流 Pao- Sah双积分模型 ,结果发现源漏电流的比例差分特性在所有的工作区域内都有谱峰特性 ,其峰值和峰位与 MOSFET的电学参数 (如有效迁移率、热电势和阈值电压等 )直接相关 .利用 PDO方法可以避免冗繁地计算双积分公式 ,并可以容易地提取出重要的 MOSFET电学参数     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Characterization for High-Performance CMOS Using In-Wafer Advanced Kelvin-Contact Device Structure

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current–voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method.      

SiGe-channel n-MOSFET by germanium implantation

The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported. The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared. The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs. For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall. The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher     

Generalized saturation analysis for submicron MOSFETs and MODFETs

This paper presents a comprehensive generalized saturation analysis for submicron MOSFETs and MODFETs. An analytical expression for the saturation voltage of submicron MOSFETs is proposed. The dependence of the saturation voltage of short-channel MOSFETs on both the gate voltage and the channel length has been extensively studied. A comparison is made among conventional, numerical and proposed saturation voltages. The proposed model is acceptable as compared with the numerical data. Similar observations of the saturation-voltage dependence on both the gate voltage and the channel length have been obtained for MODFETs. These obtained similarities between MODFETs and MOSFETs suggest that the analysis is applicable to all field effect transistors where a conducting channel is created between a source region and a drain region.     

全电流模型的比例差分特性

用比例差分算符(PDO)方法研究了长沟MOSFET在各个工作区域(亚阈区和饱和区)的比例差分特性．利用PDO方法研究全电流Pao-Sah双积分模型,结果发现源漏电流的比例差分特性在所有的工作区域内都有谱峰特性,其峰值和峰位与MOSFET的电学参数(如有效迁移率、热电势和阈值电压等)直接相关．利用PDO方法可以避免冗繁地计算双积分公式,并可以容易地提取出重要的MOSFET电学参数．     

A review of recent MOSFET threshold voltage extraction methods

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET.     

Increased hot-carrier effects using SiGe layers in verticalsurrounding-gate MOSFETs

The use of silicon germanium (SiGe) heterostructures in vertical surrounding gate MOSFETs provides an additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device. Incorporation of an SiGe layer in the vertical MOSFET drain can modify hot-carrier characteristics via material dependent impact ionization coefficients. MOSFETs with ramped SiGe drain layers showed increased drain current in the soft breakdown regime, due to increased impact ionization as verified by substrate current measurement, with up to 1.5 V decreases in breakdown voltage. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior without costly expenditures of time, material, and equipment     

A novel technique to determine the gate and drain bias dependentseries resistance in drain engineered MOSFETs using one single device

A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived     

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

An accurate analytical threshold voltage model is presented for fully-depleted SOI n-channel MOSFETs having a metal-insulator-semiconductor-insulator-metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Since the inversion charge is proportional to the drain current at low bias, the model is self-consistent with the measurement scheme when the threshold voltage is measured as the gate voltage at which the variation of the transconductance at low drain bias is maximum. Numerical simulations show good agreement with the model with less than 3% error.