Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths

This article presents experimental results for a clock-timing methodology that allows timing characterization and testing of high-speed pipelined datapaths using slow-speed testers. The technique uses a clock-timing circuit to control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9 ps in 0.18 μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit used to generate and control test mode clocks.     

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.     

A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

Clock generation and distribution for the first IA-64microprocessor

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market     

CMOS集成时钟恢复电路设计

该文设计了一个集成时钟恢复电路,恢复时钟的频率为125MHz。通过采用电流相减技术等补偿措施,很大程度上降低了振荡器的压控增益,从而在不影响电路性能的前提下大大地降低了芯片面积。本设计采用0.25m标准CMOS工艺实现,有效芯片面积小于0.2mm2,功耗仅10mW。在各种工艺角、温度以及供电电源条件下的仿真结果均表明,该电路相位偏差小于200ps,时钟抖动的峰峰值小于150ps。该文对一个采用本时钟恢复电路的100MHz PHY系统进行流片、测试,验证了时钟恢复电路能够正常工作。     

X-tolerant Test Data Compaction with Accelerated Shift Registers

Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.     

A low-power half-delay-line fast skew-compensation circuit

A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-/spl mu/m CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600/spl sim/800 MHz, as designed, with a power consumption of 25/spl sim/36 /spl mu/W/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively.     

单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

针对单光子探测盖革雪崩焦平面读出电路应用,基于全局共享延迟锁相环和2维H型时钟树网络,该文设计一款低抖动多相位时钟电路.延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块,引入差分电荷泵结构,减小充放电流失配,降低时钟抖动.采用H时钟树结构,减小大规模电路芯片传输路径不对称引起的相位差异,确保多路分相时...     

Detailed Theoretical and Experimental Characterization of 10 Gb/s Clock Recovery Using a Q-Switched Self-Pulsating Laser

A detailed characterization of the clock recovery properties of a self-pulsating, three-section distributed feedback laser is presented by directly comparing simulation and experimental results for the dependence of the RMS timing jitter of the recovered clock signal on important properties of the input signal. These properties include the duty cycle, peak power, extinction ratio, state-of-polarization, optical signal-to-noise ratio (OSNR), and waveform distortion due to residual group velocity dispersion and polarization mode dispersion. The permissible range for each of these is identified in terms of the RMS timing jitter of the recovered clock signal being less than 2 ps. In particular, the self-pulsating laser is effective for input signals degraded by amplified spontaneous emission noise as it provides this level of jitter performance for input OSNRs larger than 8.8 dB (0.1 nm noise bandwidth).     

An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s.     

一种AD9371宽带无线同步定时模块简化方法

在满带宽100 MHz条件下,AD9371的收、发采样频偏问题严重,不采用精确的同步定时模块时,在高斯白噪声信道下测试,误码率较调制误差公式erf值偏高.传统的Gardner定时同步算法虽能降低采样频偏,但Gardner算法的实现复杂度太高.针对这对性能和复杂度间的矛盾,给出了一种同步定时模块的现场可编程门阵列(Fie...     

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55?nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3?GHz, and the test precision is about 35?ps at the typical process corner with supply voltage 1.0?V and temperature 25°C.     

A time digitizer CMOS gate-array with a 250 ps time resolution

A pipelined time digitizer CMOS gate-array has been developed using 0.5 μm Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10-50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion     

Retiming and reshaping function of all-optical clock extraction at 160 Gb/s in monolithic mode-locked laser diode

Retiming and reshaping behaviors in an all-optical clock extraction operation at 160 Gb/s using a monolithic 160-GHz mode-locked laser diode was investigated in detail. The investigation of the basic clock extraction performance revealed that the clock extraction was stable against the input of data signals with a long zero sequence and with a poor extinction ratio. The clock extraction performance when the input data had random intensity and timing fluctuations was also discussed. We revealed that the generated clock pulse train absorbed well the intensity and timing fluctuations of the input data. Stable clock extraction remained even when the input data had 25% of the peak-intensity fluctuations. A timing jitter reduction from 0.85 to 0.32 ps was also achieved. The detailed investigation in the frequency-domain analysis of the jitter spectra revealed that the timing jitter reduction originated from the short-term stability of the slave 160-GHz mode-locked laser diode.     

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.     

一种基于全数字锁相环的SRAM实速测试方案

提出了一种采用实速测试方式测试SRAM性能参数及可靠性的方案。该方案在内建自测试(BIST)电路的基础上,通过增加一个超高速ADPLL为SRAM性能的实速测试提供一个高频时钟,同时还加入延时链来产生不同相位的4个时钟。通过调整这4个时钟的相位来获得SRAM的关键性能参数,如存取时间、地址建立和保持时间等。该方案在UMC 55nm CMOS标准逻辑工艺下流片验证。测试结果显示,SRAM最大测试工作频率约为1.3GHz,测试精度为35ps。     

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.     

Polarization-, Wavelength-, and Filter-Free All-Optical Clock Recovery in a Passively Mode-Locked Laser Diode With Orthogonally Pumped Polarization-Diversity Configuration

We proposed and demonstrated all-optical clock recovery system using a monolithic mode-locked laser diode (MLLD) that operated with less sensitivity to the polarization and the wavelength of the input data signals also with no bandpass filter to eliminate the input signal-components. The keys to this new technique are the MLLD integrated with a tensile-strained quantum-well saturable absorber and a new polarization-diversity setup by signal input orthogonally polarized to the lasing polarization of the MLLD. This approach was experimentally validated in the 40 Gbps clock recovery experiments. The results exhibited excellent performance of the clock recovery with low timing jitters (<0.3 ps) remaining small dependence on the wavelength and the polarization of the input data signals and input-signal suppression less than -30 dB with no use of the bandpass filter. We also succeeded in the stable clock recovery for the input of polarization-scrambled data signals.