Single damascene integration of porous Zirkon™ version 1 low-k dielectric films

Zirkon™ LK2000 version 1 dielectric film (Zirkon™ is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO₂ CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O₃), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH₃, N₂/O₂) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.     

Porous low k film with multilayer structure used for promoting adhesion to SiCN cap barrier layer

For 28 nm technological node, porous ultra low dielectric constant (p-ULK) film has been used as an insulator in Cu interconnection in the back-end of the line (BEOL). The interfacial adhesion between p-ULK film and SiCN (nitrogen doping silicon carbon) cap barrier layer played the important role for the package, wiring bond, chip package interaction (CPI), peeling, and reliability. In this work, the thin initial oxide and thin transition films were deposited in situ before depositing p-ULK film, which was used for improving the interfacial adhesion between p-ULK film and SiCN film, The ULK film with multilayer structure was characterized by secondary ion mass spectroscopy (SIMS) for examining multilayer structure, focused ion beam (FIB) and transmission electron microscope (TEM) for observing interface, and four-point bending (4-PB) for testing interfacial adhesion. Results indicated that the interfacial adhesion was obviously improved by adding initial oxide and transition layer before the deposited p-ULK film, which hardly impact the capacitance using single layer structure.     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Electrical and physical characterization of remote plasma oxidized HfO/sub 2/ gate dielectrics

Bi-layer gate stacks consisting of a HfO/sub 2/ and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400/spl deg/C due to radical oxygens, leading to an improvement in the quality of HfO/sub 2/ with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO/sub 2/-like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO/sub 2/-like interface demonstrate RPO as a promising way for gate-stack optimization.     

Chemically Homogeneous Complex Oxide Thin Films Via Improved Substrate Metallization

A long‐standing challenge to the widespread application of complex oxide thin films is the stable and robust integration of noble metal electrodes, such as platinum, which remains the optimal choice for numerous applications. By considering both work of adhesion and stability against chemical diffusion, it is demonstrated that the use of an improved adhesion layer (namely, ZnO) between the silicon substrate and platinum bottom electrode enables dramatic improvements in the properties of the overlying functional oxide films. Using BaTiO₃ and Pb(Zr,Ti)O₃ films as test cases, it is shown that the use of ZnO as the adhesion layer leads directly to increased process temperature capabilities and dramatic improvements in chemical homogeneity of the films. These result in significant property enhancements (e.g., 300% improvement to bulk‐like permittivity for the BaTiO₃ films) of oxide films prepared on Pt/ZnO as compared to the conventional Pt/Ti and Pt/TiO_x stacks. A comparison of electrical, structural, and chemical properties that demonstrate the impact of adhesion layer chemistry on the chemical homogeneity of the overlying complex oxide is presented. Collectively, this analysis shows that in addition to the simple need for adhesion, metal‐oxide layers between noble metals and silicon can have tremendous chemical impact on the terminal complex oxide layers.     

A selective CMP process for stacked low-k CVD oxide films

A chemical mechanical polishing process for a stacked low-k dielectric material, which is suitable for inter-metal dielectric applications, has been developed. The dielectric is deposited by CVD and composed of a methyl-doped silicon oxide (i.e., low-k Flowfill) embedded between thin SiO₂ layers. A new CMP parameter is introduced, which is the removal rate selectivity between two different kinds of materials. We were able to adjust the selectivity between cap and low-k Flowfill layer in a range between 3:1 and 1:5 by tuning the slurry mixture. Different test structures were used to investigate the effect of the removal rate selectivity on the planarisation efficiency of the CMP process. A higher removal rate of the low-k Flowfill layer in comparison to that of the cap layer results in a significant increase of the planarisation length and a reduction of the overpolish needed to achieve planarity.     

Adhesion studies of CVD copper metallization

The adhesion of chemical vapor deposition (CVD) Cu thin films to various barriers was observed to improve with a post-deposition anneal or a physical vapor deposition (PVD) Cu flash layer on the barrier before depositing CVD Cu. The ambient exposure of the barrier before the deposition of CVD Cu has been observed to lead to degradation of adhesion in both CVD Cu seed and CVD/PVD Cu high vacuum integrated metallization schemes. The integrated CVD and PVD Cu deposition scheme exhibits better adhesion due to the inherent annealing provided during the PVD deposition which is carried out at temperatures between 300 and 400°C. We have evaluated both qualitative and quantitative tests — tape test, Stud pull test and 4-point bend test — in understanding adhesion and observed that each of these tests give different details of interface breakdown.     

Poly(5-nitroindole) Thin Film as Conductive and Adhesive Interfacial Layer for Robust Neural Interface

Poly(3,4-ethylenedioxythiophene) (PEDOT) has emerged as a promising neural interface material, but the weak adhesion of PEDOT to substrates adversely affects its reliability and practical application. Although adhesive interfacial layers have been explored to enhance the adhesion of PEDOT, their poor conductivity seriously compromises the performance of neural electrodes. It is a great challenge to develop an adhesive interfacial layer with excellent electrical properties. Herein, utilizing the advantages of polyindole derivatives, conductive polymers which have various functional groups for potential interface bonding, a conductive, adhesive, and biocompatible poly(5-nitroindole) (PIN-5NO₂) interfacial layer is developed to enhance the adhesion of PEDOT to metal electrodes. The conjugated PIN-5NO₂ with its superior electrical property can be prepared by electropolymerization of 5-nitroindole; however, the electrografting of amino groups, which is reduced from nitro groups in 5-nitroindole can provide strong adhesion with the gold (Au) substrate. With PIN-5NO₂ as an adhesive interfacial layer, the resultant Au/PIN-5NO₂/PEDOT electrode exhibits excellent electrochemical property, superb stability, and biocompatibility for high-performance neural interface. The in vivo evaluation of Au/PIN-5NO₂/PEDOT electrocorticographic microelectrodes demonstrates superior capacity to capture the neural dynamics of the brain. The novel strategy would offer a new insight for the construction of high-performance neural electrodes with high stability for neural interface application.     

A study on charge reduction in HfO/sub 2/ gate stacks

Charge in metal-organic chemical vapor deposition-grown HfO/sub 2/ gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO/sub 2//interfacial layer (IL) interface and positive at the Si/IL interface. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces both interface charge greatly. The FGA can also significantly reduce the hysteresis and interface state density. The effects of post deposition anneal at various temperatures and under various ambients have also been studied. It is found that a high-temperature dilute oxidizing ambient anneal followed by an FGA reduces the charge at both interfaces.     

Copper/Polyimide Heterojunctions: Controlling Interfacial Structures Through an Additive‐Based,All‐Wet Chemical Process Using Ion‐Doped Precursors

Heterojunctions comprising copper thin films and polyimide underlayers are exploited as an important system for generating flexible microelectronic circuit elements. A fully additive‐based chemical method that allows metallization of polyimide films with copper by the in situ reduction of copper ions doped in surface‐modified polyimide precursors is reported. It is shown that dimethylamine borane is a good reducing agent for copper ions initially complexed with carboxylate anions in the hydrolyzed polyimide layers. This reduction allows diffusion of copper ions towards the film surface to form copper thin films, and simultaneously controls the fabrication of interfacial microstructures between the copper and underlying polyimide. The formation of copper thin films and composite layers is elucidated by glow‐discharge optical emission spectrometry depth profiling, scanning electron microscopy, and cross‐sectional transmission electron microscopy studies, and it is shown that the final microstructure at the copper/polyimide interface is dependent upon experimental variables: a larger amount of copper ions incorporated into the modified layers and a higher reduction rate result in the formation of a granular layer containing smaller copper nanoparticles near the film surface. The granular layers thus formed are found to play a critical role in achieving strong adhesion between metal thin films and the substrate, owing to the increased contact area and hence the increased work of adhesion between them. These results have important implications for realizing a novel adhesion scheme between deposited metals and underlying dielectrics based on nanoscale interlocking through metal nanoparticles.     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage     

Interfacial Chemistry of InP/GaAs Bonded Pairs

The interfacial chemistry of InP/GaAs direct bonding with either 5% HF in water or HF:ethanol (1:9) chemical pretreatments was investigated. Multiple internal transmission-Fourier transform infrared spectroscopy (MIT-FTIR) and atomic force microscopy (AFM) were used to probe the bonding interface. The bond strength was measured as a function of annealing conditions and prebonding chemical treatment. The HF-based pretreatments remove the initial native oxide, leaving an interfacial layer of either water or ethanol. The initial room-temperature bond strength is primarily determined by the strength of hydrogen bonding, which, in turn, is a function of the prebonding treatment. The removal of interfacial water and ethanol, and with the subsequent formation of the oxide layer, leads to an increased bond strength. For ethanol-based HF treatments, ethanol appears to react with the underlying interfacial oxide layer through a complex interaction with the absorbed water. After annealing, the bond strength for all prebonding preparations can reach a high value, comparable to the fracture strength of the InP. The oxide composition after thermal annealing shifts from In₂O₃ to the eventual thermodynamic equilibrium product, InPO₄.     

Analysis of Cu/Low-k structure under back end of line process

As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global-local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global-local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process.     

Role of a nucleation layer in suppressing interfacial pitting in

In this work, we investigate the role of a low temperature nucleation layer on the interfacial properties of InAs epilayers grown on (100) semi-insulating InP substrates using a two-step metalorganic chemical vapor deposition method. Cross-sectional and plan-view transmission electron microscopy studies were carried out on InAs films of nearly equal total film thicknesses but for different thicknesses of a nucleation layer of InAs deposited at low temperature on the substrate. Our studies show that thermal etchpits are created at the interface between the InAs film, and the InP substrate for thin nucleation layer thicknesses. This is because the low temperature nucleation layer of InAs does not cover completely the surface of the InP substrate. Hence, when the temperature is raised to deposit the bulk of the InAs film, severe thermal pitting is observed at the interface. These thermal etchpits are sources of threading dislocations. To obtain high quality InAs films and suppress interfacial pitting there is an optimum thickness of the nucleation layer. Also, our studies show that there is a relationship between the density of defects in the film and the thickness of the nucleation layer. This in turn relates to the variation of the electronic properties of the InAs films. We have observed that for all nucleation layer thicknesses, the density of threading dislocations is higher close to the interface than at the free surface of the film.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

Homogeneous degradation of surface emitting type InGaAsP/InP lightemitting diodes

The homogeneous degradation modes of InGaAsP/InP light-emitting diodes (LED) with either a Au-Zn ohmic type or a Ti/Pt/Au Schottky type p-side electrode are discussed. In LEDs with a Au-Zn electrode homogeneous degradation goes through two distinct stages: an initial period of very slowly decreasing optical output power followed by a period of rapidly decreasing optical output power. Both modes are caused by electrode metal diffusion and alloy reactions between the electrode and the cap, cladding, and active layers during aging. In Ti/Pt/Au electrode LEDs homogeneous degradation is accompanied by a series resistance increase, which is caused by the formation of In- and Ga-depleting interfacial layers between the electrode and the cap layer. This study indicates that homogeneous degradation depends on the interface stability between the p-side electrode and the cap layer     

Influence of Annealing and Interfacial Roughness on the Performance of Bilayer Donor/Acceptor Polymer Photovoltaic Devices

Through controlled annealing of planar heterojunction (bilayer) devices based on the polyfluorene copolymers poly(9,9‐dioctylfluorene‐co‐bis(N,N′‐(4,butylphenyl))bis(N,N′‐phenyl‐1,4‐phenylene)diamine) (PFB) and poly(9,9‐dioctylfluorene‐co‐benzothiadiazole) (F8BT) we study the influence of interface roughness on the generation and separation of electron–hole pairs at the donor/acceptor interface. Interface structure is independently characterized by resonant soft X‐ray reflectivity with the interfacial width of the PFB/F8BT heterojunction observed to systematically increase with annealing temperature from 1.6 nm for unannealed films to 16 nm with annealing at 200 °C for ten minutes. Photoluminescence quenching measurements confirm the increase in interface area by the three‐fold increase in the number of excitons dissociated. Under short‐circuit conditions, however, unannealed devices with the sharpest interface are found to give the best device performance, despite the increase in interfacial area (and hence the number of excitons dissociated) in annealed devices. The decrease in device efficiency with annealing is attributed to decreased interfacial charge separation efficiency, partly due to a decrease in the bulk mobility of the constituent materials upon annealing but also (and significantly) due to the increased interface roughness. We present results of Monte Carlo simulations that demonstrate that increased interface roughness leads to lower charge separation efficiency, and are able to reproduce the experimental current‐voltage curves taking both increased interfacial roughness and decreased carrier mobility into account. Our results show that organic photovoltaic performance can be sensitive to interfacial order, and heterojunction sharpness should be considered a requirement for high performance devices.     

Group IVB metal oxides high permittivity gate insulators depositedfrom anhydrous metal nitrates

The electrical performance of column IVB metal oxide thin films deposited from their respective anhydrous metal nitrate precursors show significant differences. Titanium dioxide has a high permittivity, but shows a large positive fixed charge and low inversion layer mobility. The amorphous interfacial layer is compositionally graded and contains a high concentration of Si-Ti bonds. In contrast, ZrO₂ and HfO ₂ form well defined oxynitride interfacial layers and a good interface with silicon with much less fixed charge. The electron inversion layer mobility for an HfO₂/SiO_xN_y /Si stack appears comparable to that of a conventional SiO₂ /Si interface     

Optimization of n/i and i/p buffer layers in n-i-p hydrogenated microcrystalline silicon solar cells

Hydrogenated microcrystalline silicon (μc-Si:H) intrinsic films and solar cells with n-i-p configuration were prepared by plasma enhanced chemical vapor deposition (PECVD). The influence of n/i and i/p buffer layerson the μc-Si:H cell performance was studied in detail. The experimental results demonstrated that the efficiency is much improved when there is a higher crystallinity at n/i interface and an optimized a-Si:H buffer layer at i/p interface. By combining the above methods, the performance ofμc-Si:H single-junction and a-Si:H/μc-Si:H tandemsolar ceils has been significantly improved.