LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively     

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (V_DD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s     

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-μm CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V_pp differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz±250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V_pp and up to 70 MHz with 0.7 V_pp. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm² active area, fabricated in 0.35-μm CMOS     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphasering oscillator

A general ring oscillator topology for multiphase outputs is presented and analyzed. The topology uses the interpolating inverter stages to construct fast subfeedback loops for long chain rings to obtain both multiphase outputs and higher speed operation. There exists an optimum number of inverter stages inside a subfeedback loop which gives the highest oscillation frequency. A fully integrated 1.25-GHz 0.35-μm CMOS phase-locked-loop clock generator that incorporates the proposed voltage-controlled oscillator topology was designed and implemented for a data transceiver. It provides eight-phase outputs and achieves RMS tracking jitter of 11 ps from a 3.3-V power supply     

A family of low-power truly modular programmable dividers instandard 0.35-μm CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 μm bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider     

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm,3.5-nm Tox, 1.8-V CMOS technology

This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation     

A switched-current, switched-capacitor temperature sensor in0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT δV_BE signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25° from -55°C to 125°C with an error of less than 1°. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 μA. The supply voltage is 2.7-5.5 V     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

0.3-μm mixed analog/digital CMOS technology for low-voltageoperation

A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation has been demonstrated, including a new MOSFET structure with laterally doped buried layer (LDB) and a double-polysilicon capacitor with low voltage coefficient. The LDB-structure MOSFET provides constant threshold voltage which is independent of channel length, high current drivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the top polysilicon plate and a Si₃N₄ capacitor-insulator, despite the insulator thickness being scaled down to oxide-equivalent 20 nm     

Quaternary logic circuits in 2-μm CMOS technology

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm², is timed with a 2.2-MHz clock, and consumes 93 mW of power     

GSM transceiver front-end circuits in 0.25-μm CMOS

So far, CMOS has been shown to be capable of operating at radio-frequency (RF) frequencies, although the inadequacies of the device-level performance often have to be circumvented by innovations at the architectural level that tend to shift the burden to the circuit building blocks at lower frequencies, The RF front-end circuits presented in this paper show that excellent RF performance is feasible with 0.25-μm CMOS, even in terms of the requirements of the tried-and-true superheterodyne architecture. Design for low-noise and low-current consumption targeted for GSM handsets has been given particular attention in this paper. Low-noise amplifiers with sub-2-dB noise figures (NFs) and a double balanced mixer with 12.6 dB single-sideband NF, as well as sub-25-mA current consumption for the RF front end (complete receiver), are among the main achievements     

ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHzdigital ECL data transmission systems

The design of a full-CMOS circuit that converts voltage signals from those used for emitter-coupled logic (ECL) to CMOS and vice versa, for use in digital data transmissions with clock frequencies up to 150 MHz, is described. Extremely high performances are obtained due to a novel circuit principle, in both the ECL-to-CMOS convertor and the CMOS-to-ECL convertor. A wideband CMOS amplifier used in the ECL-to-CMOS convertor, incorporating a current injection technique to increase the bandwidth of the circuit, is also presented. A circuit principle is presented to realize an extremely fast CMOS-to-ECL conversion, based on a current switching technique and charge injection to compensate the large output capacitance. Both circuits make use of replica biasing to ensure maximum switching speed in the ECL-to-CMOS convertor and correct ECL output levels in the CMOS-to-ECL convertor. An ECL-CMOS-ECL repeater has been designed in a 1.2-μm double-metal CMOS process     

Ensemble Monte Carlo simulation of a 0.35-μm pseudomorphic HEMT

Theoretical analysis and precise comparison to experiment of the performance of a 0.35-μm pseudomorphic Al_0.15Ga_0.85 As/In_0.15Ga_0.85As high-electron-mobility transistor (HEMT) are presented. The calculations are made using an ensemble Monte Carlo simulation with the unique inclusion of real space transfer as well as the full details of the two-dimensional electron gas, velocity overshoot, and ballistic transport, and the effects of the two-dimensional electric field profile. The calculated current-voltage characteristic is compared to recent experimental measurements showing excellent agreement to within ~10% over a full range of gate and drain biases. It is found that near the source, the two-dimensional system dominates the transport physics, while near the pinch-off point, the effects of real space transfer become apparent. It is further determined that the high-speed performance of the pseudomorphic HEMT stems predominantly from the high electron confinement within the two-dimensional system, and the high electron mobility and confinement within the gamma valley in the bulk InGaAs     

An advanced 0.5-μm CMOS disposable TiN LDD/salicide spacerprocess

An advanced 0.5-μm CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N^- and boron P^- regions for improved short-channel behavior     

Nonsilicide source/drain pixel for 0.25-μm CMOS image sensor

A nonsilicide source/drain pixel is proposed for high performance 0.25-μm CMOS image sensor. By using organic material spin coat and etch back, silicide is only formed on poly gate which can be used as interconnection, not for source/drain region that solve the optical opaqueness and undesirably large junction leakage of silicide. The performance of MOSFET changes little due to the high sheet resistance of nonsilicide source/drain. With H₂ annealing and double ion implanted source/drain junction, the dark current can be further reduced. The novel pixel (three transistors, 3.3 μm×3.3 μm, fill factor: 28%) shows low dark current (less than 0.5 fA per pixel at 25°C) and high photoresponse     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

High-voltage devices for 0.5-μm standard CMOS technology

The feasibility of the smart voltage extension (SVX) technique featuring complementary high-voltage devices without any modifications of the process steps of an 0.5-μm standard CMOS technology is discussed here. This letter focuses on the optimization of the breakdown voltage of the HVNMOS as well as the possible implementation of the HVPMOS. Different high-voltage options with increasing process modification steps are discussed as a function of the required high-voltage capabilities