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本文描述了一种32×32位快速并行结构乘法器,介绍了基于修正布斯编码算法的部分积产生电路,并对部分积的符号扩展进行了简化.给出了基于4 ∶ 2压缩器的华莱士树的实现方法,在最后的快速进位链中采用64位快速超前进位加法器以提高乘法器的运行速度.并用PSPICE 仿真工具对其进行了功能验证和仿真.通过仿真分析比较,该32×32位乘法器的速度比传统的32位基于Wallace/Dadda的乘法器的速度快18.9%. 相似文献
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本文介绍了一种符合IEEE754浮点标准的全流水结构的32位浮点乘法器,在该浮点乘法器中,提出一种Booth编码的华莱士树压缩结构,减小了关键路径延时,明显地提高了浮点乘法器的性能,且结构更规则,易于VLSI实现。整个设计采用Verilog HDL语言结构级描述实现。 相似文献
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在传统数字PID控制器中,计算占据了大量的时间。因此,在很多场合需要一种运算速度很高而同时又具有高性能价格比的硬件实现形式。本文首先给出了一种实现有符号数相乘的并行定点乘法器设计方案,在此基础上提出了高速数字PID控制器的ASIC设计方案,随后介绍了控制器的版图设计以及逻辑模拟,结果证明设计是成功的。 相似文献
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本文提出了一种新型的双重多斜模数转换乘法器。该乘法器能够克服时分割乘法器的零点漂移问题和满度测量的漂移问题。用在直流功率测量时,对串模干扰有较强的抑制能力。另外,该乘法器还克服了双重双斜乘法器在零区容易锁死的问题。不必分别调整四个象限系数,使调整步骤大大简化。由于该乘法器使用一个基准源,所以电路简单,成本低,调整方便。双重多斜乘法器采用了积分原理,对非线性具有补偿作用,理论上与双重双斜乘法器线性度在同一数量级。与采样技术和数值处理技术相结合,该乘法器还可以用于交流功率的测量。 相似文献
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针对配电网故障信息出现异常尤其是不可识别异常而导致误判的问题,提出了一种基于网络树状图和改进D-S证据理论的配电网故障定位新方法。该方法的突出优点在于使用多源信息进行故障定位,可避免因单源信息发生异常导致的误判。首先提出了一种新的基于网络树状图的搜索算法,该算法利用配电网故障时产生的故障指示器信息、配变报警信息和电话投诉信息建立相应的网络树状图,并通过搜索网络树状图进行故障初步定位。然后利用改进D-S证据理论将每种故障信息的定位结果进行信息融合,得到最终的定位结果。实例结果表明所提方法有效、可行,可以解决故障信息出现不可识别异常时的定位问题。 相似文献
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Sa'ed Abed Bassam Jamil Mohd Zaid Al‐bayati Sahel Alouneh 《International Journal of Circuit Theory and Applications》2012,40(11):1175-1185
Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed. This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high‐order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus‐II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power‐delay product in 32‐bit multipliers. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献
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Stefania Perri Marco Lanuzza Pasquale Corsonello 《International Journal of Circuit Theory and Applications》2014,42(7):731-743
This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
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《IEEJ Transactions on Electrical and Electronic Engineering》2017,12(Z2):S113-S119
We propose a novel conceptual structure of a large‐scale wave energy converter (WEC) and develop an electrical design method for tubular permanent magnet linear generators (PM‐LGs) adopted in the WEC. We describe the electrical design method of the PM‐LGs in detail, with design results of 1 MW PM‐LGs presented. Magnetic flux distribution obtained by the simulation is further analyzed, which shows good agreement with the design results. The electrical design method of large‐scale PM‐LGs described in this paper provides a reference to design large‐scale electric machines. 相似文献