2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

Penalty-free 2.5 Gbit/s photonic switching using a semiconductorfour-gate-array module

A penalty-free photonic switching experiment at 2.5 Gbit/s using a gate-array module of four semiconductor optical amplifiers, flip-chip-mounted on a silicon motherboard and provided with highspeed electronic drivers, is reported for the first time. Switching times shorter than 400 ps are obtained, allowing for guardbands as short as two bits between consecutive cells     

60 Gbit/s宽带电路交换ASIC芯片设计

文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案.针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案.同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据.     

1 Gbit/s high-speed bit-synchronisation LSI for B-ISDN

The CCITT recommended that the bit rates for synchronous digital hierarchy (SDH) should be multiples of 155.52 Mbit/s. In handling high-speed data (such as 622.08 Mbit/s) in B-ISDN switching systems, there are problems associated with waveform degradation caused by impedance mismatching and amplitude attenuation. A countermeasure is the regeneration of the distorted waveforms using the system clock in each board. A bit-synchronisation circuit allows distorted waveforms to be regenerated and simplifies the design of timing between boards. The author have developed a high-speed bit-synchronisation LSI with excellent jitter tolerance in the 600 Mbit/s region and which has a simple circuit structure. The LSI features a circuit structure based on an elastic store, Si-bipolar super self-aligned process technology (SST),/sup 1/ and careful timing design. It can handle three different bit-rates (622.08, 155.52, and 51.84 Mbit/s) and has a maximum bit rate of 1 Gbit/s.<>     

32 Gbit/s multimode fibre transmission using high-speed, low current density 850 nm VCSEL

Error free transmission over multimode fibre at data rates up to 3 2 Gbit/s at 25degC and 25 Gbit/s at 85degC using an oxide confined 850 nm VCSEL biased at a current density of 11-14kA/cm² is demonstrated. The VCSEL is optimised for high-speed by reducing capacitance and self-heating and by using strained InGaAs quantum wells for high differential gain.     

Cell processing LSIs for 2.4 Gbit/s SDH-based ATM transmission system

Introduces cell processing large-scale integrated circuits (LSIs) suitable for byte-oriented systems operating at 2.4 Gbit/s. The LSIs are based on a newly proposed cell delineation circuit which uses a pipeline processing technology to realise byte-by-byte shift operations, an error-detect and error-correct circuit and a descrambling circuit. Prototype LSIs, constructed with a super-selfaligned process technology (SST), are tested at up to 3.7 Gbit/s.<>     

10 Gbit/s optical receiver module using plastic package

A novel optical receiver module using a plastic package, a glass V-groove substrate, an edge-illuminated refracting facet photodiode and a Si bipolar preamplifier IC has been developed. Its signal lines were designed using a three-dimensional electromagnetic field analysis. For a fabricated module, a frequency response of 7.7 GHz and a sensitivity of less than -14 dBm at 10 Gbit/s were achieved     

All-optical Gbit/s switching using nonlinear optical loop mirror

The switching of a 20 Gbit/s pulse train at 2.5 Gbit/s in an all-fibre NOLM is demonstrated. An entirely semiconductor case powered configuration was used with a long loop (6.4 km) ensuring low power (10 mW) for the switching pulses.<>     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.<>     

25 Gbit/s selector module using 0.2 mu m GaAs MESFET technology

A high-speed selector module has been developed. It is constructed from a selector IC mounted in a ceramic package, a power supply unit, phase shifters, and coaxial cables. The IC was designed using LSCFL and fabricated with 0.2 mu m gate length GaAs MESFETs. The selector module operated above 25 Gbit/s. It is expected to be applied to high-speed IC measurements.<>     

40Gbit/s RZ-DQPSK Transponder模块的技术研究

文章重点介绍了40Gbit/sRZ-DQPSK(归零码-差分正交相移键控)Transponder模块的组成和关键技术,针对发射端和接收端控制给出了合理的实验方案。通过眼图、星座图以及光信噪比试验进行验证,眼图良好,光信噪比为12.3dB。实验结果表明,采用该方案设计出的光模块的参数能满足标准要求,可以应用于光通信领域。     

86 Gbit/s SiGe receiver module with high sensitivity for 160/spl times/86 Gbit/s DWDM system

A 86 Gbit/s SiGe receiver chip with an on-chip phase-locked loop and a preamplifier is presented. The chip is mounted and measured in a module assembly with RF-connectors. At the intended system data rate of 86 Gbit/s bit-error-free operation at a high input sensitivity of 50 mV/sub pp/ is demonstrated. With an external clock, high-speed capability is proven by error-free operation up to 100 Gbit/s     

40 Gbit/s XOR and AND gates using polarisation switching within 1 m-long bismuth oxide-based nonlinear fibre

The implementation of all-optical logic gates of XOR and AND operable at 40 Gbit/s using polarisation switching within only 1 m length of a fabricated Bi-NLF is experimentally demonstrated. The two logic functions are obtained in a single device by simply changing the polarisation states of input signals relative to that of a probe beam.     

High sensitivity 5 Gbit/s optical receiver module using Si IC and GaInAs APD

A 5 Gbit/s optical receiver module was developed by using a wideband transimpedance Si IC and a high gain-bandwidth product GaInAs APD. A 6 GHz bandwidth Si IC utilising a f/sub t/=20 GHz Si MMIC process, bare chip mounting of a Si IC and an APD to minimise parasitic capacitance, made it possible to realise high speed operation and high receiver sensitivity of -31.8 dBm.<>     

Dual-in-line laser diode module for fiber-optic transmission up to 4 Gbit/s

A very high-speed laser diode (LD) module, having a "butterfly" type dual-in-line structure is developed. This LD module consists of a laser diode, a p-i-n-photodiode for monitoring the laser power, a thermoelectric cooler, and a thermistor. The power emitted from the LD is coupled into a single-mode fiber using a hemispherical tapered fiber technique. The microwave design of the LD module employing high frequency equivalent circuit and scattering (S) parameters is shown. Parasitic inductances and capacitances in the LD module degrade the high frequency characteristics. This is a very serious problem in gigabit fiber-optic transmission systems. The microwave impedance, small signal high frequency characteristics, and high-speed pulse response of the fabricated module with low parasitics are also shown. Electrical resonance frequency is 4.8 GHz and well opened eye patterns up to 4 Gbit/s are obtained in the experiments.     

640 Gbit/s (32×20 Gbit/s) WDM transmission with 0.4(bit/s)/Hz spectral efficiency using short-period dispersion-managedfibre

640 Gbit/s (32 channel×20 Gbit/s) WDM transmission with 0.4 (bit/s)/Hz spectral efficiency is demonstrated using short-period dispersion-managed fibre (Perfect Cable^TM). The average Q-factor was measured to be better than 18 dB after transmission over 280 km     

10 Gbit/s based NRZ DWDM systems using polarisation switching in single wavelength channel

It is experimentally demonstrated that the nonlinear tolerance of 10 Gbit/s/ch NRZ based DWDM systems over 1500 km standard singlemode fibre can be significantly improved through the use of orthogonal polarisation switching between adjacent bits in a single wavelength channel.     

1 Gbit/s PSK homodyne transmission system using phase-lockedsemiconductor lasers

Homodyne detection of 1 Gb/s pilot-carrier (BPSK) optical signals using phase-locked 1.5 μm external-cavity semiconductor lasers is discussed. After 209 km fiber transmission of a 2¹⁵-1 pseudorandom binary sequence (PRBS), the measured receiver sensitivity is 52.2 dBm or 46 photons/bit. Experimental evidence of the data-to-phase-lock crosstalk that potentially limits the usable ratio of linewidth to bit rate in pilot-carrier PSK homodyne systems is presented