A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

A 6-bit 3.5-GS/s flash ADC is reported. A load circuit with a clamp diode and a replica-biasing scheme is developed for low-voltage and high-speed operation. An acceleration capacitor is introduced for high-speed overdrive recovery of a comparator. An averaging and interpolation network is employed in this ADC. The interpolation factor is optimized considering random offset, active area, and systematic offset to realize low offset and small active area. The ADC is fabricated in a 90-nm CMOS process and occupies 0.15 mm². It consumes 98 mW with a 0.9-V power supply. With Nyquist input, SNDR and SFDR at 3.5 GS/s are 31.18 dB and 38.67 dB, respectively.     

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.     

1 GHz 8位闪烁A/D转换器中的比较器设计

文章从工艺偏差的角度入手，采用蒙特卡罗分析方法，结合独特的辅助电压源前置放大器，基于TSMC0.25μmCMOS工艺，对1GHz采样率8位A／D转换器中的比较器进行了设计，使之具有实际流片的可靠性。该比较器实现了单数据比较时间小于1ns，比较精度在2mV以内，数据整体延时1ns。     

A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS

This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background calibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6$ {rm V}_{rm pp}$ input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73 $~$dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250$~$mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68 $~$pJ per conversion-step.      

A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS

A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10^-11 at 4 GS/s.     

1-V电源65nm GP CMOS工艺下一款十位80MS/s 1.6mW逐次逼近型模数转换器

This paper presents a 10-bit 80-MS/s successive approximation register(SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip(SoC).By using the top-plate-sample switching scheme and a split capacitive array structure,the total capacitance is dramatically reduced which leads to low power and high speed.Since the split structure makes the capacitive array highly sensitive to parasitic capacitance,a three-row layout method is applied to the layout design.To overcome the charge leakage in the nanometer process,a special input stage is proposed in the comparator.As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock,and a tunable clock generator is implemented.The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP(general purpose) CMOS technology.Measurement results show a peak signal-to-noise and distortion ratio(SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit(FOM) of 94.8 fJ/conversion-step.     

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 ${hbox{mm}}^{2}$ in a 90 nm 1P9M digital CMOS process.      

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

A 1-V, 8-bit successive approximation ADC in standard CMOS process

A 1-V 8-bit 50-kS/s successive approximation analog-to-digital converter (ADC) implemented in a conventional 1.2-μm CMOS process is presented. Low voltage, large signal swing sample-and-hold, and digital-to-analog conversion are realized based on inverting op-amp configurations with biasing currents added to the op-amp negative input terminal so that the op-amp input common-mode voltages can be biased near ground to minimize the supply voltage. At the same time, the input and output quiescent voltages can be set at half of the supply rails. A low-voltage latched comparator is realized based on the current-mode approach. The entire ADC including all the digital circuits consumes less than 0.34 mW. An effective number of bits of 7.9 was obtained for a 1-kHz 850-mV peak-to-peak input signal     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS

Two frequency-translating hybrid analog-to-digital converters (FTH-ADCs) are implemented using building blocks that are designed and fabricated in a 90-nm CMOS technology. These blocks include a mixer, a filter, and an ADC that are cascaded to build each analog processing path of the FTH-ADC. The mixer-filter path is designed with sufficient linearity and signal-to-noise-and-distortion ratio (SNDR) to accommodate for the desired resolution of the path ADC. A 4-bit flash ADC structure is used in each path. This path has a signal bandwidth of 0.5 GHz and frequency-translates the input signal into baseband and digitizes it with the sample rate of 2 GHz. Multiple such mixer-filter-ADC paths are then combined together with proper mixing frequencies in order to implement two- and three-channel ADC systems. The two- and three-channel systems have overall input bandwidths of 2 and 3 GHz and effective conversion rates of 4 and 6 GS/s, respectively, while maintaining their single-path resolution across their entire input bandwidths. The implemented architecture provides an extendible solution to improve the speed of ADCs by incorporating them in an FTH-ADC architecture.     

A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply     

A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

CMOS analog-to-digital converters (ADC's) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V_GS plus one V_DSsat between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-μm CMOS occupies an area of 2.4×2 mm² and consumes 10 mW each in analog and digital supplies     

A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$mu$m CMOS

In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13- $mu{hbox {m}}$ CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique is used to prevent disturbance at the beginning of the residue amplification. The reduction of the MDAC output swing by enhancing the accuracy of CADC increases the output devices' over-drive voltage and decreases output loading. The proposed design methods allow closed-loop MDAC to operate at high speed while maintaining low power consumption. The measured SFDR, SNR, and SNDR are 40.7 dB, 33.8 dB, and 33.7 dB, respectively, at the Nyquist rate input. The ADC power dissipation is 49 mW and corresponds to a figure-of-merit (FoM) of 1.24 pJ/conv.-step. The active area occupies 0.16$~{hbox {mm}}^{2}$.      

A 10-Bit 500-MS/s 55-mW CMOS ADC

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a high-speed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55$~$mW from a 1.2-V supply.      

一种12位100 MS/s流水线ADC的设计

设计了一种12位100 MS/s流水线型模数转换器。采用3.5位/级的无采保前端和运放共享技术以降低功耗;采用首级多位数的结构以降低后级电路的输入参考噪声。采用一种改进型的双输入带电流开关的运放结构,以解决传统运放共享结构所引起的记忆效应和级间串扰问题。在TSMC 90 nm工艺下,采用Cadence Spectre进行仿真验证,当采样时钟频率为100 MS/s,输入信号频率为9.277 34 MHz时,信干噪比(SNDR)为71.58 dB,无杂散动态范围(SFDR)为86.32 dB,电路整体功耗为220.8 mW。     

一种1MS/sCMOS/SIMOX8位A/D转换器

采用CMOS/SIMOX工艺制作1Msam ple/s 8 位A/D转换器。该A/D转换器采用半闪烁型结构,由两个4 位全并行A/D转换器实现8 位转换。电路共有31个比较器,采用斩波稳零型结构,具有结构简单和失调补偿功能。电路由2100 个器件组成,芯片面积为3.53 m m ×3.07 m m     

A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.     

A CMOS 8-Bit High-Speed A/D Converter IC

A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.