关于生成有向图的全部有向回路的回路向量空间法

本文提出一个由有向图的(1)有向回路基集或(2)定向回路基集,通过线性组合,生成全部有向回路的算法。文中证明了一条点数边数相等原则。根据此原则,得到一个识别有向回路的简单方法,从而使算法的计算时间与对应的无向图算法基本相同。     

生成有向图的有向通路和有向回路的一个新算法

本文首先定义了顶点的边,度关系矩阵,由此形成通路矩阵。证明了通路矩阵生成有向通路和有向回路的条件,提出了一个系统地,无重复地生成有向的全部有向通路和向回路的新算法。     

每一个自然网孔都是一个独立回路的证明

证明每一个网孔都是一个独立回路的方法不止一种。这里仅介绍一种证明方法。我们知道,在选回路时,每选一个都含有一条为先选的回路所没有走过的新支路,则这样所选的回路就保证是独立的。对于任何平面网络,我们总可以做到每取一个网孔都将至少包含一条新支路。图1所示为一任意的平面网络,我们总可以由外逐步向里地将它划分为若干层次:第Ⅰ层次为所有边缘网孔;第Ⅱ层次为与第Ⅰ层次的网孔有公共支路的所有网孔;第Ⅲ层次为与第Ⅱ层次的网孔有公共支路的所有网孔;其余依此类推,直     

生成有向图的有向回路基集及全部有向回路的一个搜索算法

本文证明了几个关于有向图基本性质的定理。在此基础上,提出一个同时生成有向图的有向回路基集和全部有向回路的算法。该算法能系统地、无重复地和成组地产生全部有向回路。从而解决了求有向回路基集的有效算法问题。     

光集成回路

所谓光集成回路和电子集成回路一样,是在光波段把包括激光源等在内的光回路集成为一个整体而成。最近才明确提出“光集成回路”这一名称。本文就光集成回路的现状和存在问题略加说明。     

由於第三回路终端反射使回路间增加的串音

本文指出,在实际情况下,所有“第三”回路的两端全部绝緣,由於第三回路終端处电流与电压波的反射,使回路間的近端和远端串音都大大增加。所得到的計算回路交叉的公式就是考虑进这项串音的。文中並提出由第一个增音机输出端到另一个增音机输入端經由第三回路所生串音的计算方法。     

钢线回路互相间以及与有色金属回路间的串音防卫度

本文研究了有色金属回路对钢线回路的串音以及铜鲢回路互相间距由第三有色金属回路的串音。同时指出,当钢线回路上装置有杂音抑制设备以及在正确地设计回路交叉程序的情况下,架挂在缆旭上的所有钢线回路都可以用来开通高频三路载波电话。     

变电站二次回路的故障分析及查找方法

变电站二次回路是电气系统一个重要组成部分,二次回路发生故障,直接影响电气设备乃至电力系统的安全运行,甚至造成极其严重的后果。因此,变电站二次回路一旦发生故障,应迅速、准确的作出判断排除故障,如何迅速、准确的查找和处理二次回路的故障。结合我多年从事变电站二次回路和试验工作经验,总结出一杏可行的故障处理方法。     

电子音频调谐回路

在电子电路中,经常会遇到调谐回路.但一般看到的都是高频调谐回路,很少看到音频调谐回路.这倒并不是电路中不需要低频调谐回路,而是制作音频调谐回路时,需要用大的电感器和大容量的可变电容器.现在能见到的大容量可变电容器有CB-2-1100型空气双连可变电容器,两组并联使用最大容量也不过2200微微法.如果谐振电路的谐振频     

一个改进的量子隐形传态回路

量子隐形传态是一种典型的量子通信方式,它用经典辅助的方法来传送量子态,并引入了量子纠缠的特性.实现隐形传态的量子回路形式有很多,为了更有效地传递量子态,本文在Brassard回路的基础上提出一个改进的量子回路,它具有更简洁的结构,并能实现量子隐形传态.     

AN EFFICIENT CIRCUIT VECTOR SPACE ALGORITHM FOR GENERATING ALL DIRECTED CIRCUITS OF A DIGRAPH

An efficient circuit vector space algorithm is presented for enumerating directed circuits ofa directed graph,by which every directed circuit is generated by the ring sum of a fundamental circuit anda subset of the obtained directed circuits,and can be expressed as a linear combination of a basic set of thedirected circuits.     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现 ,提出具有信息恢复能力的静态绝热 CMOS记忆电路 .认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体 ,由主触发器集合和从触发器集合相互连接构成 ,其中含有输出和反馈从触发器 .采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离 .还设计出 5 4 2 1BCD码 10进制和 7进制可变计数器 (带有进位输出从触发器和反馈清 0从触发器 ) ,用计算机模拟程序检验电路的正确性     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现,提出具有信息恢复能力的静态绝热CMOS记忆电路.认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体,由主触发器集合和从触发器集合相互连接构成,其中含有输出和反馈从触发器.采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离.还设计出5421BCD码10进制和7进制可变计数器(带有进位输出从触发器和反馈清0从触发器),用计算机模拟程序检验电路的正确性.     

基于划分的力矢量布局算法

提出了一个全新的基于划分的力矢量布局算法．针对大规模集成电路的布局问题，采用基于并行结群技术的递归划分方法进行分解解决，并结合改进的力矢量算法对划分所得的子电路进行迭代布局优化．通过对MCNC标准单元测试电路的实验，与FengShui布局工具相比，该布局算法在花费稍长一点的时间内获得了平均减少12%布局总线长度的良好效果．     

A New Design Method for Self-Checking Unidirectional Combinational Circuits

In this paper, a new method for the design of unidirectional combinational circuits is proposed. Carefully selected non-unidirectional gates of the original circuit are duplicated such that every single gate fault can only be propagated to the circuit outputs on paths with either an even or an odd number of inverters. Unlike previous methods, it is not necessary to localize all the inverters of the circuit at the primary inputs. The average area over head for the described method of circuit transformation is 16% of the original circuit, which is less than half of the area overhead of other known methods. The transformed circuits are monitored by Berger codes, or by the least significant two bits of a Berger code. All single stuck-at faults are detected by the method proposed.     

Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X–Y Zoning Method: Case Study

We propose a method of diagnosing analog circuits that is achieved by combining an operation-region model and an X–Y zoning method. The X–Y zoning method can be used to detect faults in analog circuits by using the relationship between circuit inputs and outputs. The operation-region model can be used to analyze/model circuit behaviors by utilizing changes in the operation regions of MOS transistors in a circuit. Operation regions are obtained from transistor node voltages at sampling time corresponding to a particular excitation of the input value and the corresponding output value. Since we developed a data processing method to handle data discretely, we could implement a procedure for diagnosis based on the preset test, which is a method of diagnosing digital circuits. We demonstrated the effectiveness of our method by applying it to ITC’97 benchmark circuits with hard and soft faults. We found that the diagnostic resolution is one for every fault.     

Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.     

Optimised multiply/accumulate architecture for very high throughputrate digital filters

A new modified circuit for implementing high performance IIR filters based on a pipelined multiply-accumulate (MAC) processor is proposed. Clever deployment of latches in the circuit allows the results to be generated once every cycle thereby providing increased performance with reduced size and power consumption over previously designed circuits     

Simultaneous Two-Way Data Transmission Over a Two-Wire Circuit

Simultaneous two-way (full-duplex) data transmission in the same bandwidth normally requires separate channels, and in the telephone network is realized by using a four-wire circuit. This paper reports on investigations directed toward full-duplex operation on a two-wire circuit using a hybrid coupler and a passband automatic transversal filter at each end of the circuit to separate the two signals. Full-duplex binary transmission at a rate of 2000 Bd in each direction has been experimentally demonstrated on a limited number of twowire circuits. Photographs of eye patterns are provided to illustrate the substantial improvement over operation with hybrids alone. Limitations on performance due to unstable distant echoes are described.