非挥发性记忆体Read Disturb测试方法的研究

DDF是一种高容量的NAND Flash。以DDF产品为例,研究和讨论了它的Read Disturb测试方法。受测试时间的限制,只能选择局部的存储区间进行DDF的Read Disturb测试。这样局部区间的测试结果是否能够代表整个芯片的性能,设计了一套实验,对这个课题进行了研究和讨论。依据非挥发性记忆体产品的特性,主要以阈值电压的分布为参考来评价DDF芯片性能的一致性和性能恶化趋势的一致度。最后的实验结果证明了这种测试方法的正确性和合理性。这种分析方法也可以用于其他非挥发性记忆体产品的其他可靠性测试项目的评估。     

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

一种适用于射频电子标签的超低功耗嵌入式EEPROM

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

SONOS存储器中隧穿氧化层淀积预清洗工艺研究

介绍了当今业界流行的两种隧穿氧化层淀积预清洗工艺:改进的RCA预清洗工艺以及HF-last预清洗工艺。通过实验对比各自优缺点,分析差异产生的根本原因。相对于改进的RCA预清洗工艺,HF-last预清洗工艺使SONOS存储器阈值电压窗口增大约600 mV。但可靠性测试结果表明,HF-last工艺会降低器件的耐烘烤和耐擦写循环能力。进一步的电荷泵对比实验结果表明,HF-last工艺引起的耐烘烤和耐擦写循环能力的降低,分别由Si-SiO₂界面态增加和隧穿氧化层变薄引起。     

安捷伦与北大合建SoC测试教育中心和SoC测试工程中心

新成立的北京大学-安捷伦科技SoC测试教育中心是华北地区首家系统级芯片测试教育中心.该中心可向在校学生和半导体工程师们提供集成电路测试的系统培训和教育服务,为中国半导体产业的发展提供急需的专业人才.而新成立的北京大学-安捷伦科技SoC测试工程中心,将采用曾成功测试中国第一颗国产32位CPU芯片的安捷伦93000 SoC测试系统,为北京地区提供对含有微处理器、高速数字、内嵌式内存和模拟信号等各种复杂组合的SoC测试能力,为北京地区及周边的集成电路设计公司提供一流的SoC测试服务.     

强电磁干扰下射频集成微系统防护的挑战与机遇

强电磁脉冲注入到射频集成芯片/微系统中将产生一系列连锁响应,影响系统、器件以及芯片工作状态甚至引起击穿等可靠性问题,严重威胁器件、电路及系统安全。传统的电磁脉冲防护依赖于前后门的系统级别防护,将电磁防护设计与风险控制机制引入早期设计阶段至关重要。集成电路芯片是国家重大基础设施的核心部件,射频集成微系统的抗电磁脉冲攻击能力对系统安全有着举足轻重的作用。该文介绍了强电磁干扰下集成电路防护的挑战,从强电磁脉冲损毁机理、能力评估与测试技术、防护技术等方面介绍了该领域国内外的研究动态,分析了当前研究存在的主要问题和机遇,旨在为芯片级的电磁安全防护提供参考。     

集成电路圆片级可靠性测试

在集成电路制造厂的工艺监控体系中引入可靠性监控对于控制产品的可靠性十分重要.圆片级可靠性测试技术通过对集成电路产品的工艺过程进行可靠性检测,能够为集成电路制造工艺提供及时的可靠性信息反馈.圆片级可靠性测试通常是采用高加速应力对各种可靠性测试结构进行测试,以实现快速的工艺可靠性评价.对半导体集成电路圆片级可靠性测试的背景、现状和发展趋势进行了概况和探讨,介绍了目前在VLSI生产中应用最为广泛的栅氧化层经时击穿、电迁移和热载流子注入效应的可靠性测试结构.     

铝铜合金对LED芯片电极可靠性的影响

发光二极管(LED)芯片反射电极中铝的稳定性对芯片的可靠性至关重要,少量铜的加入可改善铝的耐电流性.理论计算了电子柬蒸镀沉积时,镀源和镀膜中铜质量分数的对应关系.对纯铝和不同铜质量分数的铝铜合金进行了金属线耐电流测试和薄膜反射率测试,并对纯铝或铝铜合金电极的LED芯片进行了老化测试.结果表明,相对于纯铝电极结构,铜质量分数为2％的铝铜合金电极在几乎不影响反射率的前提下,可显著提高电极的耐电流性能.以铝铜合金为电极的LED芯片在老化过程中,可有效阻止铝的电迁移,从而显著提升了LED芯片的可靠性.     

极大规模集成电路测试开发平台和全自动测试线全面建成并投入产业化应用

北京确安科技股份有限公司通过国家科技重大专项（02专项）项目“极大规模集成电路测试技术研究及产业化应用”,全面建成了极大规模集成电路测试开发平台和全自动测试线,实现了300 mm (12英寸)晶圆产业化测试,具备了每月550片12英寸晶圆测试和每月50万颗高密度封装形式的高端芯片成品测试能力。     

集成电路自动测试设备的维护与保养

芯片测试作为集成电路的最后一道环节，在集成电路发展的链条中处于非常重要的位置。在整个芯片测试过程中，保证芯片测试的精确性、准确性和可靠性，准确定位筛选出具有缺陷的芯片显得格外重要。为了避免因自动测试设备造成芯片测试数据的不准确性，定期对集成电路自动测试设备进行维护与保养十分重要。从工程实际出发，从计量校准、参数能力验证和设备检修方面，阐述集成电路自动测试设备的维护与保养，并对管理要求和注意事项进行了总结，为行业人员提供了有益的参考。     

A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memory's external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage V_TH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.     

Metal nanocrystal memory with high-/spl kappa/ tunneling barrier for improved data retention

A nonvolatile memory (NVM) with metal nanocrystal (NC) embedded in high-/spl kappa/ dielectrics is proposed. With the larger work function of the metal NC compared to that of silicon NC, the metal NC memory exhibits the better data retention characteristic. The theoretical analysis showing the effect of the electron barrier height on tunneling current density is also presented to support the importance of work function engineering of the NC in NVM structure. The other electrical characteristics such as the programming transient and data endurance are also studied and described in this paper.     

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory(NVM) are investigated. A good performance of the memory cell has been achieved,including a fast program/erase(P/E) speed under low voltages,an excellent data retention(maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10%after 10~4 P/E cycles.The data show that the device has strong potential for future embedded NVM applications.     

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.     

可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

Refinement of Unified Random Access Memory

This paper investigates how gate height $(H_{g})$, which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower $H_{g}$ yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower $H_{g}$ shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM.      

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 $ muhbox{m}^{2}$. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 $hbox{rm{AA}}$, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.      

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Indium-tin-oxide,free, flexible,nonvolatile memory devices based on graphene quantum dots sandwiched between polymethylsilsesquioxane layers

Indium-tin-oxide (ITO) free, nonvolatile memory (NVM) devices based on graphene quantum dots (GQDs) sandwiched between polymethylsilsesquioxane (PMSSQ) layers were fabricated directly on polyethylene terephthalate (PET) substrates by using a solution process technique. Current-voltage (I-V) curves for the silver nanowire/PMSSQ/GQD/PMSSQ/poly(3,4-ethylenethiophene):poly(styrene sulfonate)/PET devices at 300 K showed a current bistability. The ON/OFF ratio of the current bistability for the NVM devices was as large as 1 × 10⁴, and the cycling endurance time of the ON/OFF switching for the NVM devices was above 1 × 10⁴ s. The Schottky emission, Poole-Frenkel emission, trapped-charge limited-current, and space-charge-limited current were dominantly attributed to the conduction mechanisms for the fabricated NVM devices based on the obtained I-V characteristics, and energy band diagrams illustrating the “writing” and the “erasing” processes of the devices.