一种实现数模混合电路中的DAC测试的BIST结构

由于超大规模集成电路技术的快速进步,测试数模混合电路变得越来越困难．针对DAC的测试问题,采用了一种内建自测试（BIST）的测试结构,用模拟加法器把电压测量转换成时间测量的方法,分析并给出了如何利用该结构计算DAC的静态参数．利用该方法,既可以快速得到DAC的静态参数,又提高了测试精度,使得测试电路简单、紧凑和有效．     

谱分析方法的混合电路BIST

SoC芯片内对于混合信号电路测试有着举足轻重的作用.本文介绍了一种通过谱密度分析方法的混合电路内建自测试.此方法通过使用噪声源与比较器数字量化得到被测信号的频谱特性.它的主要特点是电路简单、抗干扰性能强和多点插入多路并行采集,不需要多位AD转换器和多路选择开关.此方法基本上是全数字式的,采用一位量化,数据处理速度快,能满足给定条件下的实时处理要求;并可利用系统内已有的资源,适应于SoC环境.本文给出了系统实现的详细结构和一个测试锁相环电路的测试仿真实例,验证了谱分析方法的测试有效性.     

一种用于高精度ADC片上测试的信号发生器

随着模/数转换器（ADC）性能的提高,如何用最有效的方法对ADC进行准确而快捷的测试,成为当今研究的热点问题。提出了一种应用于高精度ADC片上测试的高精度高线性度模拟三角波信号发生器。该信号发生器由方波积分器和迟滞比较器反馈控制电路组成,可为精度高达14 b的模/数转换器的静态特性测试提供足够精度的片上测试激励。仿真结果表明,该信号发生器所生成的三角波电压范围为82 mV~1.719 V,周期为366 μs,INL小于24 μV,等效精度达到16 b以上,具有非常高的线性度,并且可根据所需要的周期和幅度进行方便而有效的调整。     

一种有效的双矢量测试BIST实现方案

文章提出了一种简单有效的双矢量测试BIST。实现方案．其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法，该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测，证明了该方案在计算量和硬件开销方面的优越性。     

一种低功耗BIST测试产生器方案

低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案，该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑，对LFSR的输出和时钟进行调整，从而得到了准单输入跳变的测试向量集，使得待测电路的平均功耗大大降低，给出了以ISCAS'85/89部分基准电路为对象的实验结果，电路的平均测试功耗降幅在54．4％－98．0％之间，证明了该方案的有效性。     

数模混合电路的工艺开发

本文简要说明了数模混合电路工艺平台的建立过程中，单项工艺的开发和工艺集成的建立。     

数模混合电路的PCB设计

高速PCB的设计中,数模混合电路的PCB设计中的干扰问题一直是一个难题。尤其模拟电路一般是信号的源头,能否正确接收和转换信号是PCB设计要考虑的重要因素。文章通过分析混合电路干扰产生的机理,结合设计实践,探讨了混合电路一般处理方法,并通过设计实例得到验证。     

数模混合电路PCB的电磁兼容设计

数模混合信号电路PCB的设计很复杂,元器件的布局、布线以及电源和地线的处理将直接影响到电路性能和电磁兼容性能。本文系统地介绍了数模混合信号电路设计时的注意事项及在实际应用中所采取的优化电路性能的措施。     

Aqilent混合信号测试解决方案——ADC的测试

1前言 模拟/数字信号转换器(ADC)和数字/模拟转换器(DAC)是两种基本的电子应用模块,用于实现模拟和数字信号之间的转换.作为独立器件或者集成到各种混合信号芯片中,广泛的应用于各种电子产品.因此,在对这些混合信号芯片进行测试的时候就要对其中集成的ADC/DAC的性能设计相应的测试方案.     

嵌入式系统的在线自测试技术

嵌入式系统必须满足用户对其越来越高的安全性和可靠性的要求,作者首先审视了用于测试数字系统故障的各种在线可测试技术,然后重点讨论了一种将被广泛应用于嵌入式系统的在线测试技术－内建自测试技术。     

一种混合信号SoC中模数转换器的内建自测试方案

提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.     

BIDES: A BIST design expert system

BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.Now with Samsung Electronics, Chase Plaza Bldg. SF, 34–35 Jeong-Dong, Choong-Ku, Seoul, Korea.     

A Novel BIST Approach for Testing Input/Output Buffers in SoCs

A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.     

Parity bit calculation and test signal compaction for BIST applications

Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included.This work was partially supported by the National Science Foundation under grant MIP-8902014.     

Testable Design and BIST Techniques for Systolic Motion Estimators in Transform Domain

Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The whole motion estimator can be viewed as a two-dimensional iterative logic array （ILA） of processing elements （PEs） and multiplying elements （MULs）. The functions of each PE and MUL are modified to be bijective to meet the M-testable conditions. The number of test patterns is 2^w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve 99.27 % fault coverage. The area overhead is about 9 %. To verify our approaches, an experimental chip is also implemented.     

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors the number of transitions in the test pattern generated by LFSR and the low transition pattern is generated for excessive transition region using an auxiliary LFSR. Experimental results for the larger ISCAS 89 benchmarks show that reduced peak power and average power can indeed be achieved with little hardware overhead compared to previous schemes.     

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits

Partial reset has been shown to have significant impact on test generation for sequential circuits in a stored-pattern test application environment. In this paper, we explore the use of partial reset in fault-independent testing and built-in self-test (BIST) of non-scan sequential circuits. We select a subset of flip-flops in the circuit to be resetable to logic one or zero during the application of the test vectors. The resetting is performed with random frequency. The selection of the flip-flops and the reset polarity is based on fault-propagation analysis, which determines the impact of a selected flip-flop on fault propagation from the circuits structure. Application of partial reset as described above yields an average improvement of 15% in fault-coverage for sequential circuits resistant to random pattern testing. To further enhance testability, we also present a methodology for selecting observable test points based on propagation of switching activity. Overall, high fault coverages (about 97%) are obtained for many of the ISCAS89 benchmark circuits. Thus, partial reset BIST provides a low cost alternative for testing sequential circuits when scan design is unacceptable due to area and/or delay constraints. The routing overhead for implementing BIST is seen to be about 6%.