二元Bent序列的前馈生成＊

通过对[1]中二元Bent序列的等价定义,本文给出了使用前馈网络生成二元Bent序列的快速方法,使二元Bent序列的产生比[2]中的方法简单,迅速。     

产生2元de Bruijn序列的一个新算法

２元ｎ级ｄｅＢｒｕｉｊｎ序列是由ｎ级移位寄存器产生的周期为２ｎ的移位寄存器序列，给出了２元ｄｅＢｒｕｉｊｎ序列的一个新的生成算法，该算法能生成２ｓ·ｇ（ｎ，ｓ）个ｎ级如ｄｅ　Ｂｒｕｉｊｉｎ序列，其中，０≤ｓ≤２（ｎ－７）／３；当 ２ｌ－１＜ｓ≤２Ｌ时，ｇ（ｎ，ｓ）＝ｎ－３Ｌ－６－［（ｎ－２Ｌ－６）／（Ｌ＋１）］。     

低速单片机驱动高速摄像头解决方案研究

由于摄像头输出图像数据量大,像素同步信号PCLK频率高,无法被众多学者所熟知的51单片机采集到。本文研究了不带FIFO缓冲器的摄像头工作原理,分析了不捕捉PCLK信号而直接采样数据的可行性,提出了以牺牲程序空间来换取执行速度的程序框架,提高了数据采集速度。为避免图像错位,提出将行中断设为高优先级。为避免采集到无效数据,指出行采集时间段必须与行中断信号高电平区间对齐。实验结果表明,51单片机运行此程序能够很好的采集摄像头图像数据,解决了低速单片机驱动高速摄像头难题,给用户带来方便的同时也节约了FIFO成本。     

Binary Sequences Derived from Dickson Permutation Polynomials over Binary Extension Field

In this paper, based on a result of Lidl and Mullen (Mathematical Journal of Okayama University, 1991), the maximum length and the second maximum length that can be attained by cycles of Dickson permutation polynomial (of the first kind) with parameter 1 are studied. Necessary and sufficient conditions for these two lengths to be attained are given, which are connected with Fermat primes and Mersenne primes, respectively. Furthermore, a class of coordinate sequences that maintains a large period is obtained, which is shown to be the coordinate sequences derived from cycles of the second maximum length. Explicit formulas for their periodicity and shift-equivalences are also presented.     

混沌二进制序列构成的安全性研究

由混沌映射驱动得到的伪随机二进制序列应确保有足够的比特安全性。信息有规律地泄漏,会导致有可能利用有限长度的输出序列完全地破译混沌驱动序列,并恢复有限长度的初始密钥,重建全部的输出序列。     

F2上2n-周期序列的k-错误序列

为了更好地刻画和研究序列的随机性,该文提出了序列的k-错误序列的概念,并对k=1,2,确定了F2上2n-周期序列的k-错误序列的计数,还给出了F2上2n-周期序列的1-错误序列个数的均值。     

费马商构造的二元序列的线性复杂度

We determined the linear complexity of a family of p² -periodic binary threshold sequences and a family of p² -periodic binary threshold sequences constructed using the Legendre symbol, both of which are derived from Fermat quotients modulo an odd prime p . If 2 is a primitive element modulo p² , the linear complexity equals to p² -p or p²-1, which is very close to the period and it is large enough for cryptographic purpose.     

二元周期序列的4-错线性复杂度

 k-错线性复杂度是衡量序列伪随机性的重要指标之一.对线性复杂度第一下降点为4的以2的方幂为周期的二元序列,本文通过分析Games-Chan算法,给出了其4-错线性复杂度的所有可能取值形式以及具有给定4-错线性复杂度的序列的计数.更进一步,给出了其4-错线性复杂度的期望.结果表明,其4-错线性复杂度的期望与线性复杂度相差不大.     

一类由交织方式构造的二元ZCZ序列簇

2000年, Tang, Fan和Matsufuji给出(L,M,Zcz)-ZCZ序列簇的理论界为ZczL/M-1 。给定正整数n和L,本文给出一个交织ZCZ序列簇的构造算法,该算法由L条周期为L的正交序列簇生成一类(2n+1L,2L,2n-1)-ZCZ序列簇。若n2且4 |, 该类ZCZ序列簇中编号为奇数的序列与编号为偶数的序列在移位为时相关值为零。此外,选择不同的正交序列簇或不同的移位序列, 经构造算法可以生成不同的ZCZ序列簇。     

The 2-error Linear Complexity of 2n-Periodic Binary Sequences

Linear complexity and k-error linear complexity of the stream cipher are two important standards to scale the randomicity of key sequences. For a random 2n-periodic binary sequence, the number of sequences with given 2-error linear complexityis provided. Then the expected 2-error linear complexity of a random 2n-periodic binary sequence is given.     

并元互补二元序列族的布尔函数刻划

本文首先给出了并元互补二元序列族与一类布尔函数族的等价关系，然后采用布尔函数族对并元互补二元序列族进行了研究     

一类推广的二元Legendre-Sidelnikov序列的自相关分布

推广的Legendre-Sidelnikov序列较之原序列有更好的平衡性质,但是关于该序列的周期自相关函数,迄今仅知道一些特殊移位的情形。该文利用有限域上特征和的相关性质,给出了推广的二元Legendre-Sidelnikov序列的自相关函数的完整分布。结果表明当p3(mod 4)且qp 时,推广的Legendre-Sidelnikov序列较之原序列有更好的周期自相关函数的分布。     

一种混沌序列密码的产生

受到时延混沌系统对时延时间段初值函数极端敏感特点的启发,利用一一映射与混沌映射相组合在数字滤波器的结构上产生混沌密码序列,使序列同样受到时延时间段初值的影响,增加序列的复杂度,提高保密通信的安全性,并给出了理论分析。同时对该序列的相关性等特性进行了模拟,将其与混沌跳频、非一一映射所产生的混沌序列进行比较,证明了该方法是可行性。     

一类二元序列的互相关函数

本文讨论Ｎｏ Ｓｅｑｕｅｎｃｅｓ的一种扩展的互相关特性，给出了Ｎｏ Ｓｅｑｕｅｎｃｅｓ及其扩展形式的互相关函数值与分配。     

交错并联磁集成Boost变换器在光伏发电系统中应用

文章采用了自适应模糊控制来跟踪光伏发电系统的最大功率输出点.自适应模糊控制算法比传统的模糊控制算法对如负载跳变、太阳能电池以及外部条件的改变具有更强的适应能力,能更准确的跟踪系统的最大功率输出点.光伏发电系统由太阳能电池、交错并联磁集成Boost变换器和自适应模糊控制器组成.采用交错并联磁集成技术可以减小电感的稳态相电流纹波,提高变换器的效率,同时还能提高光伏发电系统的暂态性能.自适应模糊控制方法对外界条件的改变具有更强的适应能力.最后使用了ORCAD软件对整个系统进行了仿真,并对负载突变和太阳能电池电流改变进行了仿真.仿真结果表明了采用自适应模糊控制算法可以提高光伏发电系统的总体性能.     

Classification of Random Binary Sequences Using Walsh-Fourier Analysis

The concept of a finite binary random sequence does not seem to be covered in the classical foundations of the theory of probability. Solomonoff, Kolmogorov and Chaitin have tried to include this case by considering the lengths of programs required to generate these sequences: a longer program implying more randomness. However this definition is difficult to apply. This paper presents a straightforward procedure using Walsh functions to determine the pattern in a binary sequence. A quantitative measure of randomness has also been proposed. This has been defined as the number of independent data (via the Walsh transform) required to generate the sequence divided by the length of the sequence. However at present this classification procedure is restricted to sequences of length 2k only. When extended to infinite sequences it yields results agreeing with those by the classical probability theory.     

二元GMW序列Niho采样下的互相关性分析

GMW序列是一种线性复杂度很高的非线性序列,在直接序列扩频系统中有着很好的应用前景.通过证明级联二元GMW序列与其采样序列的互相关性在特定条下和构造级联GMW序列的幂无关,将二元GMW序列与其采样序列的互相关性与m序列联系起来.通过现有二元m序列在Niho采样下的互相关性研究结论,分析证明了级联二元GMW序列在Niho采样下的互相关性具有四值、五值、六值特性.     

一种改进型交织ZCZ序列族的设计

本文提出了一族长ZCZ区间序列构造方法,此方法在已有基于交织方法构造ZCZ序列基础之上,通过m次递归构造,在保持序列数目M不变的条件下,序列的零相关区宽度和序列长度都变成了原序列的Mm倍,相比于以往方法得到的序列在零相关区宽度和序列长度上都得到了扩展.这些序列族可用于近乎同步CDMA系统中.     

Low-Power High-Speed Hybrid Wave-Pipeline Architectures for Binary Morphological Dilation

Dilation and erosion are two fundamental operations of mathematical morphology for image processing. This paper presents three hybrid wave-pipeline (HWP) architectures for real-time binary dilation operator. With minor changes to the number and/or to the type of the basic gates, they can be employed as erosion operator. In the first HWP-architecture, each single cell utilizes the wave technique along with delay units for balancing the data paths. By minimizing the number of delay units, the second HWP-architecture with reduced power consumption and hardware complexity is obtained. The third HWP-architecture employs wave technique in each three cascaded cells. This architecture improves the above performance further, at the cost of slight reduction in maximum clock frequency and clock frequency range. Simulation results, using a 0.18 μm CMOS technology, indicate that the HWP architectures have higher speed, less hardware complexity, and lower power consumption compared to pipeline (P) architecture. Also, they are faster than wave-pipeline (WP) architecture, without the difficulty of balancing the delay of long signal paths. Simulation illustrates that the third HWP-architecture dilates a 1024 × 1024 image by a 21 × 21 structuring element (SE) in 214.64 μs. The maximum frequency of operation is 5 GHz for the power supply of 1.8 V. The power dissipation is 410 mW, and the chip area is 0.075 mm².