New methodology for localizing faults in programmable and commercial circuits

Localizing faults in integrated circuits when the CAD information is unavailable is a critical operation for failure analysis. IFA (Image Fault Analysis), a method based on the comparison of voltage contrast images is capable of offering a positive result. However, the time required for the localization can be excessive. For this reason, we have developed a methodology to insure the minimal time necessary for localization. We will present this new methodology and an application on an Altera programmable circuit.     

Synthesis of programmable multi-input current-mode linear analog circuits

This paper reports synthesis methodologies for linear analog circuits. A generalized multi-input operational transconductance amplifier (OTA) network has been synthesized that can be easily programmed to realize different analog functions. The design of the multifunction network has been realized without any switches. The inherent characteristic of OTA as a voltage-to-current (V-I) converter with differential input has been exploited in the synthesis procedure. Efficient analog circuits synthesized with programmable OTA network are reported along with simulation results. The theoretical analysis supported by extensive experimental results confirms low sensitivity, high-frequency response, and efficient programmability of the proposed OTA network to realize different types of filters.     

Metastability tests of flip-flops in programmable digital circuits

This paper describes the methods and experimental techniques for determination of the metastability behavior of the flip-flops used in the programmable digital circuits. A dual model of the metastability distinguishes two transitions at the flip-flop output (L/H and H/L) which have different impact on the Mean Time Between Failures (MTBF) of the flip-flop. A new circuit of the late transition detector (LTD) allows for determination of the pairs of the metastability parameters, the window W and the time constant τ, for both transitions. The test results are presented for four types of programmable digital circuits fabricated commercially in CMOS technology. In the all tests, the H/L transition clearly dominates with respect to MTBF (as a worse one). The presented test methods can also be used for evaluation of flip-flops in nonprogrammable digital circuits.     

THE CONTROL, DRIVE AND DISPLAY CIRCUITS ANDDEVICES IN OPTO-ELECTRONIC 2-D PROGRAMMABLE NEURAL NETWORK

In an optoelectronic 2-D programmable neural network system, optical data need to be transferred and feedback with high speed. This paper presents the design and implementation of the interface circuit and its software.     

Lifetime prediction for submicrometer LSI circuits and programmable logic: An overview

An overview is given of the experience gained in lifetime prediction for submicrometer LSI circuits and programmable logic, as reported by leading manufacturers including Siemens AG, Analog Devices, Atmel, Xilinx, Altera, QuickLogic, and Actel. The main conclusions are as follows: (i) The Arrhenius equation remains a major tool for describing the temperature dependence of circuit lifetime. (ii) The lifetime of LSI circuits continues to display a bimodal pattern. (iii) Bias-temperature stressing constitutes a generally useful technique for identifying failure mechanisms. (iv) The chi-squared distribution should be employed in predicting useful-life failure rate.Translated from Mikroelektronika, Vol. 34, No. 2, 2005, pp. 138–158.Original Russian Text Copyright © 2005 by Strogonov.     

Application-specific multiprocessor Systems-on-Chip

It often happens that designers have to integrate different instruction-set processors on a single chip. Typical applications are wireless, image processing, xDSL, network and game processors. This paper deals with the three main problems that make the design of application-specific heterogeneous multiprocessor Systems-on-Chip very hard and expensive:

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higher level specification;

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software support packages design;

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on-chip HW/SW communication design.

     

Current amplitude control circuits suitable for current-modeoscillators

A novel current amplitude control circuit suitable for current-mode oscillators is proposed. The circuit is a modified version of the well-known Gilbert gain cell. The technique obtains independent control of oscillation amplitude and small-signal current gain. As an example, the amplitude control circuit is applied to a current-mode oscillator. Simulations were carried out using HSPICE with 0.8 μm Nortel BiCMOS technology and Motorola RF transistors. Simulated results demonstrate that the nonlinear current gain control circuit behaves in a well defined manner. Low distortion and high frequency oscillations are easily obtained when the circuit is applied to a current-mode oscillator     

一种通用汽油机点火专用集成电路的设计

在对传统汽油机点火电路原理分析和总结的基础上,分析其不足并针对市场需要设计出一款点火角控制精确,一致性好,价格低廉的点火控制芯片.电路设计基于金属氧化物半导体(CMOS)工艺,采用与电源电压和工艺无关的设计,从而提高了产品的稳定性、可靠性和一致性,该电路具备完善的静电释放(ESD)设计,工作电压3～6 V,静电流小于2 mA,可广泛应用于125 mL及以下排量的汽油机中.     

Duality principle for asynchronous control circuits for directed graphs

The directed graph provides a means of analysing parallel computer structures, whether implemented in hardware or software. This letter discusses the asynchronous circuit modules used to implement the control section of such systems, and indicates a duality principle that permits a wider variety of control functions to be envisaged.     

Photovaractor for remote optical control of microwave circuits

A photovaractor for the remote optical control of microwave circuits was studied. The photovaractor was fabricated as a p-i-n photodiode placed in a pigtailed fiber optical module. The study of the impedance in the frequency range up to 3 GHz in darkness and under illumination has shown that the photovaractor capacitance strongly depends on the incident optical power. The capacitance variation of the photovaractor diode under illumination is discussed     

Two control and observation structures for analogue circuits

Two novel analogue control and observation structures which can be used to increase the testability of analogue circuits are presented. Both structures can be easily incorporated into the IEEE P 1149.4 environment to execute both DC and AC testing. The first structure consists of five switches and can perform concurrent testing. The second contains only four switches but is mainly used for off-line testing     

Ion implantation for threshold control in COSMOS circuits

The use of ion implantation for close threshold control of N-MOS and P-MOS transistors has been studied from an experimental and theoretical viewpoint. Experimental determinations of ion-implanted diffusion profiles, sheet resistivities, and threshold voltages for boron, phosphorus, and arsenic implantations are reported for doses in the range from 1 × 10¹¹to 1 × 10¹⁴ions/cm². Care has been taken to ensure accuracy of implanted dose in the 35-150 keV range in order to permit direct comparison of experiments with theory. Satisfactory agreement is observed between experiment and computer predictions using only the implantation dose and energy. The analytical model tested assumed outdiffusion in a neutral ambient from an implanted Gaussian layer. Experimental tests of the calculation are made for thresholds, sheet-resistance profiles, and amounts of dopant lost to the oxide masking layer. The theoretical model has been used as a basis for threshold control. The application of these principles is related to the practical fabrication of COSMOS circuits with close threshold control through suitable selection of starting substrate material and implantation conditions.     

Bridging dream and reality: programmable baseband processors for software-defined radio - [integrated circuits for communications]

A programmable radio baseband signal processor is one of the essential enablers of software- defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum power consumption allowed by mobile terminals is still strictly limited. These challenges require both system and architecture level innovations. This article introduces a design methodology for radio baseband processors discussing the challenges and solutions of radio baseband signal processing. The LeoCore architecture is presented here as an example of a baseband processor design aimed at reducing power and silicon cost while maintaining sufficient flexibility.     

A programmable router architecture supporting control planeextensibility

The Internet is evolving from an infrastructure that provides basic communication services into a more sophisticated infrastructure that supports a wide range of electronic services such as virtual reality games and rich multimedia retrieval services. However, this evolution is happening only slowly, in part because the communication infrastructure is too rigid. In this article we present a programmable router architecture in which the control plane functionality of the router can be extended dynamically through the use of delegates. Delegates can control the behavior of the router through a well-defined control interface, allowing service providers and third-party software vendors to implement customized traffic control policies or protocols. We describe Darwin, a system that implements such an architecture. We emphasize the runtime environment the system provides for delegate execution and the programming interface the system exports to support delegates. We demonstrate the advantages of using this system with two delegate examples     

Static Compiler Analyses for Application-specific Optimization of Task-Parallel Runtime Systems

Achieving high performance in task-parallel runtime systems, especially with high degrees of parallelism and fine-grained tasks, requires tuning a large variety of behavioral parameters according to program characteristics. In the current state of the art, this tuning is generally performed in one of two ways: either by a group of experts who derive a single setup which achieves good – but not optimal – performance across a wide variety of use cases, or by monitoring a system’s behavior at runtime and responding to it. The former approach invariably fails to achieve optimal performance for programs with highly distinct execution patterns, while the latter induces overhead and cannot affect parameters which need to be set at compile time. In order to mitigate these drawbacks, we propose a set of novel static compiler analyses specifically designed to determine program features which affect the optimal settings for a task-parallel execution environment. These features include the parallel structure of task spawning, the granularity of individual tasks, the memory size of the closure required for task parameters, and an estimate of the stack size required per task. Based on the result of these analyses, various runtime system parameters are then tuned at compile time. We have implemented this approach in the Insieme compiler and runtime system, and evaluated its effectiveness on a set of 12 task parallel benchmarks running with 1 to 64 hardware threads. Across this entire space of use cases, our implementation achieves a geometric mean performance improvement of 39%. To illustrate the impact of our optimizations, we also provide a comparison to current state-of-the art task-parallel runtime systems, including OpenMP, Cilk, HPX, and Intel TBB.

     

Application-specific Processor Architecture: Then and Now

We first relate the architecture of systolic arrays to the technological and economic design forces acting on architects of special-purpose systems some 20 years ago. We then observe that those same design forces now are bearing down on the architects of contemporary general-purpose processors, who consequently are producing general-purpose processors whose architectural features are increasingly similar to those of systolic arrays. We then describe some economic and technological forces that are changing the landscape of architectural research. At base, they are the increasing complexity of technology and applications, the fragmenting of the general-purpose processor market, and the judicious use hardware configurability. We describe a 2D architectural taxonomy, identifying what, we believe, to be a “sweet spot” for architectural research.     

Four-phase micropipeline latch control circuits

Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques     

Digitally-controlled automatic gain control circuits for CMOS CCDcamera interface

Automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems are described. The required gain of the proposed AGC is controlled directly by digital bits. The amplifying function of the AGC is divided into three stages for high-speed operation. A capacitor-segment combination technique considerably improves the effective bandwidth of the AGC. While the three-stage prototype shows 32 dB AGC dynamic range in 1/8 dB steps, the proposed two-stage AGC reduces the power and chip area further     

Adaptive thyristor power, control circuits

A solid-state circuit is described that provides electronically settable memory control (adaptive control) of thyristor power regulating devices. Electrical power delivered to ac loads, such as lighting, heating, or motors, can be smoothly varied or set to any value from zero to essentially full power by a manual, computer, or remote-controlled application of a voltage pulse to a circuit adapt terminal. Power settings of the circuit can be maintained indefinitely with or without applied power, yet they can be changed quickly (milliseconds) or slowly (dekaseconds) by the application of an appropriate adapt pulse. An adaptive ferroelectric transformer provides the analogue memory capabilities of the control circuit.