基于任意信号注入法的永磁同步电机无位置传感器FPGA实现

本文设计了一种基于任意信号注入法的永磁同步电机无位置传感器FPGA实现。任意信号注入法的原理是利用电流信号的过采样,获取一个开关周期内有效电压矢量作用时的平均电流斜率,通过电流斜率的变化率来估计转子位置。本文利用FPGA的快速采样能力和并行运算特点,对任意信号注入法进行数字化实现。通过电流过采样技术可以提高电流采样精度,改进转子位置估计精度。利用一台3kW永磁同步电机对算法进行了实验验证。     

单相并网逆变器并网电流的过采样技术

传统的数字控制逆变器采用固定的电流采样频率,导致控制性能指标受到采样时间、计算延时、数字脉宽调制(DPWM)延时的影响较大。随着DSP性价比的提高,过采样技术应用于降低延时的影响。理论上,电感电流过采样次数越多,求得的采样结果越准确,但会增加处理器的资源占用。实践证明,只要1次PWM中断进行2次电流采样,即可计算出接近电流实际平均值的采样值,从而实现比较理想的并网电流波形控制。仿真和实验验证了该方法的可行性。     

一种有源功率因数校正电流畸变抑制控制技术

为了减少风机驱动系统对电网造成的谐波污染,设计了一种带有功率因数校正功能的风机驱动器。在此项技术中,电流过零点畸变会影响功率因数校正的性能,为此提出了一种新的过零点畸变抑制方法并给出了理论证明和具体实现方式。采用占空比前馈补偿的数字控制,可以减小输入和输出电压对电感电流控制的干扰,从而使得输入电流能理想地跟踪输入电压。为了验证前馈补偿的效果,对输入阻抗进行分析进而说明了前馈补偿对电流相位超前的抑制作用。为得到准确的反馈电流,提出了一种电流采样方法,根据开关的占空比信息在一个PWM周期的两个不同时刻采样两次。文中所提出的方法可以有效抑制电流相位超前,减小电流过零点畸变,优化电流采样算法。仿真和实验结果都证明了所提出方法的正确性和有效性。     

数字锁相技术在APFC电压采样中的应用

分析了单相有源功率因数校正(APFC)电路电流畸变的原因,提出利用数字锁相环技术解决电流过零点以及峰值畸变的问题。通过旋转坐标变换完成对数字锁相环的建模,同时针对q轴分量的滤波要求,设计数字巴特沃斯滤波器,利用数字锁相环对输入电压进行采样以减小电流失真度,实现功率因数的调节。仿真和实验结果证明了数字锁相环技术在APFC电压采样中的有效性。     

基于过采样相电流重构相位误差抑制方法

传统永磁同步电机相电流重构技术在每个PWM周期内由于不同相电流采样的不同步性,会产生采样相位误差,进而对电机整体控制性能产生不利影响。在分析上述相位误差的基础上,基于传统直流母线采样方法提出了一种电流过采样策略。通过在每个PWM周期的对称采样点分别进行一次采样并取均值的方式得到该控制周期内的相电流信息,同时利用一阶保持器估计电流控制点处的电流以消除采样相位误差。实验结果证明所提出的方法能够提高相电流重构精度,具有较好的降低相电流重构技术采样相位误差效果。     

分段式虚拟过采样数字滞环控制

并网电流控制是分布式发电系统中的技术难点。在分析传统滞环控制策略的基础上,针对不对称多电平拓扑研究了一种分段式虚拟过采样并网滞环控制策略。通过将母线电压按正弦波形分段的方法,可以有效分配开关管开关频率,降低输出电流的谐波含量。在真实采样点之间插入虚拟采样点的虚拟过采样方法,解决了滞环控制中环宽失效问题。利用仿真软件对多种滞环控制策略进行对比分析,搭建实验平台对提出的算法进行实验验证。仿真与实验结果都验证了所提控制算法的正确性。     

基于DSP的磁阀式可控电抗器控制系统采样电路的设计

在磁阀式可控电抗器控制系统中,需要对电网中的电压电流进行采样。针对目前难以实时精确测量高电压、大电流这一难题,详细介绍了电力系统中高电压采样和大电流采样的设计思想,提出了基于DSP的交流采样硬件解决方案。同时,设计了相位补偿电路和过零检测电路,并给出各电路的系统试验结果。结果表明该方案解决了磁阀式可控电抗器控制系统中电压、电流采样问题以及晶闸管触发信号的基准点选择问题。     

基于HCPL-7840的直流伺服系统电流环设计

在使用PWM功放驱动的直流伺服控制系统中,电机电枢电流采样是实现电流闭环控制的关键。本文使用采样电阻和隔离放大器HCPL-7840测量电枢电流,实现了电流闭环控制和电流限幅设计,解决了电机起动电流过大引起的系统供电异常。仿真和实验结果证明该设计切实可行,对工程应用有较强的参考价值。     

基于过采样技术提高数据采集精度的新方法

在变电站恶劣的电磁环境下,当前数据采集单元的抗混叠模拟低通滤波器不能充分抑制频谱混叠,从而使测控装置性能变差.基于过采样技术,提出一种能有效抑制频谱混叠的数据采集新方法;进而,紧密结合实际讨论了运用过采样技术设计数据采集单元的相关问题;最后,通过实验对传统采样方法和过采样方法进行比较,验证了过采样方法的有效性.     

SINC滤波器时序优化与分布式电流的同步采样

研究了电机电流采样常用的SINC滤波器原理和分布式电机电流同步采样的技术难点。首先分析了SINC滤波器的FPGA时序电路和组合逻辑电路,设计了不同的时序优化方案,并对不同方案进行了仿真验证,得出最优的时序优化方案,显著缩短了SINC滤波器的延时;接着分析了分布式控制系统中,电机电流同步采样的优点及技术难点,提出了分布式电机电流同步采样的可行性方案;最后通过工程样机测试验证了SINC滤波器时序优化方案的准确性,验证了分布式电机电流同步采样方案的可行性。     

A new segmented oversampling method for imbalanced data classification using quasi‐linear SVM

Data imbalance occurs on most real‐world classification problems and decreases the performance of classifiers. An oversampling method addresses the imbalance problem by generating synthetic samples to balance the data distribution. However, many of the existing oversampling methods have potential problems in generating wrong and unnecessary synthetic samples, which makes the learning tasks difficult. This paper proposes a new segmented oversampling method for imbalanced data classification. The input space is first partitioned into several linearly separable local partitions along the potential separation boundary by introducing a bottom‐up, minimal‐spanning‐tree‐based clustering method; an oversampling method is then applied within each local linear partition to prevent the generation of wrong and unnecessary synthetic samples; a quasi‐linear support vector machine is finally used to realize the classification by taking advantages of the local linear partitions. Simulation results on different real‐world datasets show that the proposed segmented oversampling method is effective for imbalanced data classifications. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Investigating the Option of Removing the Antialiasing Filter From Digital Relays

Digital relays traditionally employ sampling rates of less than 100 samples/cycle. In order to avoid aliasing due to fault transients, these relays employ an analog antialiasing filter before critical-sampling (Nyquist rate) the input waveforms coming from instrument transformers. In many applications of electrical engineering, oversampling (greater than the Nyquist rate) has long been used to simplify the requirements of an antialiasing filter with a sharp cutoff; in some cases, the filter can even be eliminated. This paper investigates this option for a digital relay. The performance of a traditional digital relay is compared with a method that uses oversampling without using an antialiasing filter. By processing a comprehensive array of fault waveforms from Electromagnetic Transients Program simulations, a suitable oversampling rate is suggested. A comparison of phasor estimates using the traditional relay and the proposed method is made for different operating and fault conditions. The results suggest that oversampling can eliminate the antialiasing filter traditionally employed in digital relays.     

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.     

基于高倍过采样与加窗插值FFT的电力谐波分析

为提高谐波分析精度,分析了信号加窗引起的信噪比损失以及AD转换产生的量化误差,阐述了过采样技术提高信噪比的原理。在此基础上,提出了基于高倍过采样和加窗插值快速傅里叶变换(fast Fourier transform, FFT)的谐波分析方法。该方法充分利用AD转换器的潜力,以尽量高的采样速率进行AD采样,同时通过均值滤波避免高倍过采样引起的采样数据量激增问题。详细研究了所提谐波分析方法对信号中谐波分量幅值和相位的影响,并给出了简洁实用的谐波幅值和相位校正方法。仿真表明,所提方法可在不增加系统成本的前提下改善加窗插值FFT的抗噪声能力,提高谐波分析精度。     

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

基于压缩感知的低复杂度分数时延信道估计方法

基于压缩感知(compressed sensing,CS)技术的信道估计方法已被应用于正交频分复用(orthogonal frequency division multiplexing,OFDM)系统的信道估计中以提高频谱利用率。然而,传统的时域普通采样方法会导致信道测量矩阵不够精细,无法精确恢复信道状态信息。针对这一问题,提出利用分数时延信道模型模拟系统的无线多径信道,利用接收端时域过采样方法细化信道测量矩阵以提高信道估计精度。同时,为了克服由时域过采样导致的算法复杂度增加的问题,提出一种改进正交匹配追踪算法(modified orthogonal matching pursuit,MOMP)。仿真实验结果表明,在分数时延信道条件下,提出的接收端时域过采样方法能准确检测到信道的分数时延且提出的MOMP算法能显著降低估计算法的计算复杂度。     

适合集成电路实现的非均匀同步过采样谐波测量算法

从集成电路设计的角度,提出了一种基于非均匀同步过采样技术的谐波测量算法。通过合理设计过采样和降采样2个阶段中非均匀采样时钟频率的概率分布函数,使得频域的非均匀采样噪声可以被忽略。降采样得到的数据可以视为均匀同步采样的结果直接采用快速傅里叶变换进行分析,降低了对分析过程运算能力的要求。利用采样时钟的非均匀特性,大幅简化了延时锁定环路时钟产生电路的复杂度,降低了电路实现代价。仿真结果显示,算法大幅提高了谐波测量的精度。     

基于样本扩充和特征优选的IGWO优化SVM的变压器故障诊断技术

为了增强变压器故障诊断模型对不平衡样本的学习能力从而提高少数类故障样本的识别精度,提出了一种基于样本扩充和特征优选的融合多策略改进灰狼算法(improved grey wolf optimizer with multi-strategy, IGWO)优化支持向量机(support vector machine, SVM)的变压器故障诊断技术。首先,使用基于K最近邻过采样方法及核密度估计自适应样本合成算法的混合过采样技术对少数类样本进行扩充得到均衡数据集,并在此基础上采用方差分析对变压器候选比值征兆进行特征优选。然后,通过改进灰狼优化算法(grey wolf optimizer, GWO)初始化策略、参数及位置更新公式,并引入差分进化策略调整种群,提出了融合多策略的改进灰狼算法。最后,构建了一种基于混合过采样技术的IGWO优化SVM的变压器故障诊断模型,并通过多组对比实验验证了所提方法能够有效增强模型对少数类故障样本的识别能力,并提升模型的整体分类性能。     

提高感应无线位置检测分辨率的方法

感应无线位置检测技术已经广泛应用于工业机车自动化,机车全自动无人操作的精确定位,要求进一步提高位置检测分辨率。文中以感应无线车上位置检测技术为研究对象,对应用中影响检测分辨率的原因进行了分析。提出了提高检测分辨率的方法:设计一种独特的感应线圈结构,采用具有抑制干扰能力副线圈检测精密位置,并且在编码电缆的交叉处采用同一信号参数计算一般位置与精密位置而消除内部串扰的影响。实验结果表明所述方法对提高检测分辨率有明显效果。     

基于改进深度置信网络的智能电网暂态安全状态感知

深度学习是感知智能电网暂态安全状态的有效方法,针对多层重构学习过程低维特征及结构参数难以全局寻优的问题,提出了一种改进深度置信网络(Deep Belief Network,DBN)方法.首先,该方法利用SMOTE过采样算法,增加样本多样性,促使DBN深层架构的挖掘.其次,直接面向噪声样本,DBN通过网络中各神经元吉布斯...