Transformer-Coupled Power Amplifier Stability and Power Back-Off Analysis

We present a mathematical analysis of the common-mode instability and power back-off feature of a transformer-coupled Class-AB differential power amplifier (PA). The efficient impedance matching of the transformer combiner and efficiency improvement at power back-off, a major benefit of this structure, are illustrated. In addition, an analytical model is derived to predict the common-mode oscillations in PA. The analytical results, based on a simple hand-calculation model for the transistor, show good agreement with simulation results using complete 90-nm models. Two methods to suppress the common-mode oscillations are investigated and analyzed in detail.     

On the performance of the differential cascode amplifier

Analysis is made of the differential cascode amplifier stage, an amplifier made of a differential common-emitter input pair driving a differential common-base output pair referenced to the emitter potential of the input pair. The analysis shows the differential cascode amplifier to have one or more orders of magnitude increase in common-mode input resistance and common-mode rejection ratio compared to that of a conventional differential pair. Consideration is also given to the use of junction field-effect transistors for either pair in the differential cascode stage. The frequency response of the stage is studied, and a potentially troublesome common-mode complex pole pair is identified as the one disadvantage of the differential cascode circuit.     

全差分群时延可精确调节的四阶Bessel滤波器实现

采用全差分运算放大器、无源电阻以及用作可变电阻的MOS管设计实现了全差分R-MOSFET-C四阶Bessel有源低通滤波器,在所提出的电路中通过调节工作在线性区的MOS管有源电阻的阻值以抵消集成电路制造工艺过程中电阻阻值的一致性偏差,达到Bessel滤波器的群时延值得到精确设计的目的.该滤波器中所采用的全差分运算放大器不仅具备有电压共模负反馈,而且还具有电流共模负反馈,极有利于电路静态工作点的稳定.通过无源双端RLC原型低通滤波器导出的0.75μs群时延四阶Bessel滤波器,采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)、5.0V电源电压、0.5μm CMOS工艺制造,在输入信号为100kHz、2.5Vpp时,其谐波失真(THD)值低于-65dB.     

全差分可调频率四阶Chebyshev滤波器的实现

提出了一种新的全差分运算放大器,该运算放大器在具有电压共模负反馈的同时还具有电流共模负反馈,能较好地稳定其工作点。通过利用MOS管工作在线性区便能作可变电阻之用的特性,设计实现了基于R-MOSFET-C运放的全差分频率连续调节的四阶Chebyshev低通滤波器。该滤波器采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)5V电源电压、0.5m CMOS工艺生产制造。其芯片面积大小为0.36mm~2,截止频率调节范围为20kHz到420kHz,输入信号频率在100kHz,2.5Vpp时的失真小于-65dB,功耗仅为16mW。     

Transresistance instrumentation amplifier

A transresistance instrumentation amplifier (dual-input transresistance amplifier) was designed, and a prototype was fabricated and tested in a gamma-ray dosimeter. The circuit, explained in this letter, is a differential amplifier which is suitable for amplification of signals from current-source transducers. In the dosimeter application, the amplifier proved superior to a regular (single) transresistance amplifier, giving better temperature stability and better common-mode rejection.     

A high-frequency fully differential BiCMOS operational amplifier

A high-frequency fully differential BiCMOS operational amplifier design for use in switched-capacitor circuits is presented. The operational amplifier is integrated in a 3.0-GHz, 2-μm BiCMOS process with an active die area of 1.0 mm×1.2 mm. This BiCMOS op amp offers an infinite input resistance, a DC gain of 100 dB, a unity-gain frequency of 90 MHz with 45° phase margin, and a slew rate of 150 V/μs. The differential output range is 12 V. The circuit is operated from a ±5-V power supply and dissipates 125 mW. The op amp is unity-gain stable with 7 pF of capacitive loading at each output. The op amp is a two-stage, pole-split frequency compensated design that uses a PMOS input stage for infinite input resistance and an n-p-n bipolar second stage for high gain and high bandwidth. The frequency compensation network serves both the differential- and common-mode amplifiers so the differential- and common-mode amplifier dynamics are similar. A dynamic switched-capacitor common-mode feedback scheme is used to set the output common-mode level of the first and second stages     

一种新型的0．5V全差分运放的设计

提出一种新型的工作在0．5V电源电压下两级低压全差分运放,该运放结构是带有共模反馈的密勒补偿运放,拥有更强的抗噪声能力和共模电源电压抑制能力,带宽更大,提高了系统的稳定性。输入信号由晶体管的栅极加入,这点与传统的电路结构相吻合,并采用衬底自偏置解决了阈值电压对电源电压降低的限制,更易于实现。该运放结构是基于SMIC0．18μm标准CMOS工艺,HSpice仿真结果表明,这种结构的开环增益可以达到76dB,单位增益带宽150MHz。     

A Realization of a Low-Voltage Differential-Output OTA Using a Simple CM Amplifier

A technique for realization of low-voltage OTAs is presented in this letter. A very low-voltage differential-output OTA is realized by employing a new common-mode amplifier in the common-mode feedback circuit. The results of PSpice simulations are shown. The proposed OTA can operate at a 0.9 V supply voltage.     

Tunable Highly Linear Floating-Gate CMOS Resistor Using Common-Mode Linearization Technique

In this paper, an implementation of a tunable highly linear floating resistor that can be fully integrated in CMOS technology is presented. The second-order effects of a single MOS transistor operating in the triode operation regime are described, and a common-mode linearization technique is applied to suppress these nonlinearities. This technique is implemented by utilizing a low-power circuit design strategy that exploits the capacitive coupling and the charge storage properties of floating-gate transistors. The resistance of the proposed circuit is tuned by utilizing the Fowler-Nordheim tunneling and hot-electron injection quantum-mechanical phenomena. We demonstrate the use of this resistor in highly linear amplifier. We present experimental data from the chips that were fabricated in a 0.5- CMOS process. We show that this resistor exhibits 0.024% total harmonic distortion (THD) for a sine wave with amplitude. Also, we show the programmability of the amplifier gain using the proposed tunable resistor.     

下截止频率1.3～244Hz可调带通VGA设计

采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节.提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围.将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题.该VGA电路采用TSMC 0.18 μm标准工艺设计和流片,测试结果表明,1.2V电源电压下,其下截止频率调节范围为1.3～ 244 Hz,增益为49.2,44.2,39.2 dB,带宽为3.4,3.9,4.4 kHz,消耗电流为3.9 μA,共模抑制比达75.2 dB.     

差分放大电路单端输入信号的射极耦合传输及等效变换

用电路分析的方法对差分放大电路单端输入信号的射极耦合传输及等效变换进行了深入研究,目的是探索单端输入差分放大电路中输入信号的作用过程。差分放大电路的单端输入信号,经差分管的发射极耦合传输,在输入回路可等效变换为差模输入信号、共模输入信号的叠加,且等效变换时与发射极电阻Re取值大小无关,Re取值大小反映了对共模输入信号的抑制程度。所述方法的创新点是给出了单端输入信号在输入回路作用下的物理过程,完善了单端输入信号的等效变换方法。     

单端输入差分放大电路输入信号的等效变换

本文对单端输入差分放大电路发射极耦合传输的分析方法进行了深入研究,利用电路分析的方法将单端输入信号等效变换成差模输入信号与共模输入信号的叠加。指出等效变换并不需要发射极电阻Re很大的条件,Re的取值大小只反映对共模输入信号的抑制程度。并把这种方法与输入信号用数学方法等效变换进行了对比,得出这两种输入信号的等效变换方法具有等效性的结论。并介绍了单端输入差分放大电路的教学处理方法。     

全差分运算放大器中共模稳定性的分析

本文提出了用在增益可调放大器中,差分电压放大器中共模反馈稳定性的分析。本文分析了在差模运算放大器中内部共模反馈电路(CMFB)和外部由电阻构成的正反馈网络。共模反馈电路用来确保运算放大器的稳定性,外部的正反馈网络需要留心防止"锁死状态"。本文的运放采用折叠式共源共栅结构,用SMIC0.18μm混合信号工艺进行流片。     

The design of fully differential CMOS operational amplifiers without extra common-mode feedback circuits

A new fully differential CMOS operational amplifier (op amp) without extra common-mode feedback (CMFB) circuit is proposed and analyzed. In this op amp, simple inversely connected current-mirror pairs are used as active loads. From the theoretical analysis, it is shown that the common-mode signal can be efficiently suppressed by the reduced effective common-mode resistance of the active load. The proposed op amp with 2 pF capacitance loadings has an open-loop unity-gain bandwidth of 63 MHz, a phase margin 47°, and a dc gain of 67 dB in 3.5µm p-well CMOS technology. The common-mode gain at a single output node can be as low as —38 dB without extra CMFB circuit. Experimental results have successfully confirmed the capability of the efficient common-mode rejection.This work was supported by the United Microelectronics Corporation (UMC), Republic of China, under Grant C80054.     

New insight into subharmonic oscillation mode of GaAs poweramplifiers under severe output mismatch condition

This paper provides new insight into the cause of subharmonic generation in GaAs MESFET power amplifiers under severe output mismatch conditions. A nonlinear modeling methodology is developed to identify the root cause of subharmonic oscillations and provides a means to implement circuit techniques to suppress this mode of oscillation without degrading the desired power amplifier performance. The primary mechanism for low-order subharmonics generated as a result of large signal drive and severe output mismatch is shown to be parametric. This modeling-based technique is enabled through the use of a time domain MESFET model which achieves excellent convergence by avoiding the discontinuity in high-order derivatives that is typical of implementations that use conditional functions. This technique provides the design engineer for the first time the ability to determine the large signal parametric stability of a power amplifier operating into a severe mismatch and implement circuit solutions prior to MMIC fabrication     

A 40-MHz Double Differential-Pair CMOS OTA With $-{hbox{60-dB}}$ IM3

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 V_pp at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1times10^-3 mm² and the power consumption is 9.5 mW under a 1.5-V supply voltage.     

一种快速全差分CMOS运算放大器

文章在CSMC0．5μm／5V硅CMOS工艺模型下,设计了一种用于电表计量芯片的全差分运算放大器。该运放采用两级结构,其中第一级为折叠式共源共栅结构,第二级为PMOS输出缓冲结构。文章采用开关电容技术实现共模反馈以稳定输出共模电压,跟传统方法相比,这将能降低芯片面积及降低功耗。采用HSPICE软件对该电路进行仿真,仿真结果表明在负载电容为2pF情况下,该运算放大器具有开环增益为84．7dB、单位增益带宽达44．8MHz、相位裕度为67°、闭环小信号建立时间为39ns。     

Cascadable low-power gain-stabilised limiting amplifier stage

A directly cascadable low-power high-gain symmetrically limiting amplifier stage is presented. A novel technique for gain stabilisation uses a PTAT current source as an essential and inherent part of the common-mode bias feedback loop.     

Common-mode rejection limitations of differential amplifiers

The common-mode rejection ratio (CMRR) equations of the differential pair and differential cascade amplifiers are reformulated in terms of imbalances in the saturation current. Early voltage, and current gain parameters of the transport model of the bipolar transistor. The effect of source resistance on CMRR is included in the formulation. The CMRR of this class of amplifier is shown to be limited by the magnitude and imbalance of the open-circuit voltage gain of the active devices. Also, a design characteristic, common to a wider class of differential amplifiers, is shown to produce a lower bound on the attainable CMRR.     

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138 kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3 V power supply and 0.35 μm CMOS technology. Chip test results demonstrate better than −68 dB THD with 70 kHz, 2.0V_pp signal, frequency turning range of more than 14,000 from 3 Hz to 420 kHz, chip area of 0.36 mm² and power consumption of 16 mW.