Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Wafer-level BCB bonding using a thermal press for microfluidics

Benzocyclobutene (BCB) is a thermosetting polymer that can form microfluidics and bond top and bottom layers of the microfluidics at the same time, and yields high repeatability and high bonding strength. This paper reports using photosensitive BCB to fabricate microfluidics and to bond with a thermal press for 4 in. wafers. By optimizing the parameters for pattern development and using a three-stage temperature and pressure increment BCB bonding, we realize the whole wafer glass–Si or glass–glass bonding in thermal press without any crack. The wafer-level bonding shows a bonding percentage above 70%, a tensile stress above 4.94 MPa, and a bonding repeatability over 95%. Furthermore, the bonding is compatible with thick electrode integration, that microfluidics with 380 nm thick electrodes underneath can be well-bonded. Our bonding method much reduces the cost compared with bonding BCB in a wafer bonding machine. Electronic supplementary material  The online version of this article (doi:) contains supplementary material, which is available to authorized users.     

High-Precision Alignment and Bonding System for the Fabrication of 3-D Nanostructures

We successfully developed a high-precision wafer alignment and bonding system for the fabrication of a variety of 3-D nanostructures. To control the wafer positions with high accuracy during the wafer-bonding process, we improved upon a design of the conventional mask-alignment stage. A stress sensor was incorporated to measure the load between the two wafers. In addition, the parallelism of the wafers was monitored by an optical interferometry system. To determine alignment errors in both the and directions simultaneously, we devised an alignment method consisting of crossed vernier scales. We demonstrated that the new alignment and bonding system allowed us to realize precise 3-D photonic crystals with the alignment inaccuracy of < 100 nm at most, and we show that the best experimental error achieved to date was < 25 nm. As this system has the benefit of more readily and intuitively determining the absolute positions of the two wafers, it can be applied to the fabrication of a wide variety of nanoscale multilayer devices.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection

 Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting. Received: 6 July 2001/Accepted: 26 February 2002 The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann (IZM Berlin) for performance of nickel bumping process. This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides

Plain or structured hydrophillic silicon wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the wafer pairing chosen. If one or both wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the wafer surfaces just prior to bonding are described.     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Bond-quality characterization of silicon-glass anodic bonding

A simple testing method is presented that allows the comparison of the bond quality for anodically bonded wafers. An array of parallel metal lines of predetermined thickness is formed on a glass wafer. The estimation of the bond quality can be performed by visual inspection after the bonding. This method enables comparison of the anodic-bonding process performance for different glasses, for intermediate layers and various bonding conditions. The optimization of silicon-glass anodic bonding with an intermediate phosphosilicate glass (PSG) layer is shown using this technique.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential