Reconfigurable Coprocessor for Multimedia Application Domain

A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized) for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has been synthesized using Synopsys Design Compiler on a standard-cell 0.18 μ m technology. Estimated number of transistors is 335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to 95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles. Salvatore M. Carta (1997 Electronic Eng. Master. 2002 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1998 as PhD student. From 2005 he has been assistant professor in Department of Mathematics and Computer Science of the University of Cagliari. His research interests focus mainly on architectures, software and tools for embedded and portable computing, with particular emphasis on: languages, architectures and compilers for reconfigurable and parallel computing; Networks-on-chip; Operating systems for multiprocessor-systems-on-chip; low power real-time scheduling algorithms. Danilo Pani (2002 Electronic Eng. Master, 2006 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics engineering of the University of Cagliari, Italy in 2002 as Electronics and Computer Science PhD student. His primary research interests are in the area of Digital Signal Processing architectures and systems, Biomedical Engineering, Reconfigurable Systems and Cooperative VLSI architectures for distributed computing. Luigi Raffo (1989 Master, 1994 Electronics and Computer Science PhD) joined Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1994 as assistant professor. From 1998 he has been professor of Digital System Design, Integrated Systems Architectures and Microelectronics at the same Department. His research activity is mainly in the design of low-power analog and digital architectures/chips. He has been project manager of many local and international projects. He is author of more than 50 international papers in the field.     

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.     

空间太阳望远镜星载数据处理系统中的 动态可重构协处理器研究

本文提出了一种为空间太阳望远镜星载数据处理系统而设计的动态可重构协处理器方案,该方案利用4bits粒度可重构阵列将传统的基于指令流的运算方式变为基于数据流与配置流的运算方式,并通过指令流水实现了动态可重构单元与主处理器的协同工作.文章最后还给出了该方案在Xilinx XC2V3000上的实现及该实现用于乘法和1024点复数快速傅立叶变换时的性能.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.     

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

This paper presents a reconfigurable processing core architecture targeted for digital filtering applications. The architecture can be configured to execute linear phase FIR filter, DLMS adaptive FIR filter, (I)FFT, and 2D-(I)DCT with high performance and low energy consumption by reducing heavy routing resources used extensively in other reconfigurable architectures. The pipeline depth of the multipliers in the processing core is locally controlled so that power consumption is reduced by minimizing unnecessary register switching is saved. We have shown that the proposed processing core consumes less energy and has better or comparable performance than that of the existing reconfigurable architectures proposed in academia and industry, that have been tailored for these applications. The circuit is designed in 0.35-m CMOS processing technology with 3.3 V supply voltage.Sangjin Hong received the B.S. and M.S. degrees in EECS from the University of California, Berkeley and his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at Stony Brook University - State University of New York. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power reconfigurable SoC design and optimization for DSP and wireless communication systems. He has served as a member of technical committee and track chair for numerous IEEE technical conferences.Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University—State University of New Yorkin 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems.     

一种流水线ADC数字域动态可重构架构

分析流水线ADC数字域校准算法工作原理及实现电路的具体特点.为解决数字校准算法系数实时更新的问题,在PipeRench结构的基础上结合多重上下文动态可重构方式,提出了一种针对流水线ADC数字域的动态可重构电路.对该架构中的关键电路模块进行了设计并对整个电路架构进行了仿真,结果表明该架构可以实现流水线ADC数字域的动态重构.     

基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

基于DSP的FIR滤波器的C语言算法实现

有限冲激响应(FIR)滤波器是数字信号处理系统中最基本的元件,具有严格的线性相频特性,同时其单位抽样响应是有限长的,系统稳定。阐述了FIR的基本原理,并进行了MATLAB仿真。基于TI公司的TMS320VC5402 DSP硬件平台,设计了FIR低通滤波器。采用C语言算法,利用集成开发环境代码调式器(Code Composer Studio,CCS)分别观察了输入和输出波形,验证了此算法的准确性和高效性,对信号处理及信号传输有重要的研究意义。     

A General Reconfigurable Architecture for the BLAST Algorithm

The process of DNA sequence matching and database search is one of the major problems of the bioinformatics community. Major scientific efforts to address this problem have provided algorithms and software tools for molecular biologists since the early 1970s. At the algorithmic and software level BLAST is by far the most popular tool. It has been developed and continues to be maintained and distributed by the NCBI organization. The BLAST algorithm and software is computationally very intensive and as a result several computer vendors use it as a benchmark. On the other hand no systematic approach for hardware speedup of BLAST and its variants for different query and database size has been reported to date. In this paper we present our architecture that implements the BLAST algorithm for all of its major versions, and for any size of database and query. The system has been fully designed and partially implemented with reconfigurable logic. It consists of software and hardware parts and achieves a speedup of several times up to thousands of times vs general purpose computers.

一种支持同时多线程的VLIW DSP架构

本文提出了一种支持同时多线程的动态分发超长指令字(VLIW)数字信号处理器(DSP)架构。该DSP架构上可以同时运行多个线程,功能单元可以执行来自多个线程的指令,有效地提高DSP的指令吞吐率。为了使多个线程的指令更有效地调度分发到功能单元,该DSP架构还支持指令动态分发,由硬件分发单元而不是编译器来完成多线程指令的动态分配。实验结果表明,相比于单线程而言,本文提出的VLIW DSP架构可以提高功能单元利用率,隐藏存储器访问时延,使处理器的指令吞吐率平均提高约26.89%。     

面向分组密码的可重构异构多核并行处理架构

现有的可重构分组密码实现结构中,专用指令处理器吞吐率不高,阵列结构资源利用率低、算法映射过程复杂.为此,设计了分组密码可重构异构多核并行处理架构RAMCA（Reconfigurable Asymmetrical Multi-Core Architecture）,分析了典型SP（AES-128）、Feistel（SMS4）、L-M（IDEA）及MISTY（KASUMI）结构算法在RAMCA上的映射过程.在65nm CMOS工艺下完成了逻辑综合和功能仿真.实验表明,RAMCA工作频率可达到1GHz,面积约为1.13mm²,消除工艺影响后,对各分组密码算法的运算速度均高于现有专用指令处理器以及Celator、RCPA和BCORE等阵列结构密码处理系统.     

多通道阵列信号处理可重构异构SoC设计

设计实现了面向多通道阵列信号处理的可重构异构SoC。SoC集成了多通道阵列信号处理需要的多个硬件加速模块,有效提高了多通道阵列信号处理系统的计算能力。通过软件对各个算法模块的输入输出流向进行重构,达到了多通道阵列信号处理算法可重构的目的,扩展了SoC的适用范围。采用55 nm工艺进行设计,版图尺寸为6.2 mm×4.5 mm,规模约为1 000万门。流片后的测试结果验证了多通道阵列信号处理算法的有效性,证明了SoC设计的正确性。     

可配置的2D空域滤波操作VLSI架构研究

提出了一种可配置的支持红外自动目标识别应用中不同窗口操作的2D空域滤波类操作VLSI架构,从SoC角度考虑能够更好地满足不同的图像处理应用．该架构与已报道的对于该类操作的其他结构解决方案进行比较,新结构具有较高的处理速率．新结构在SIMC0．18μmCMOS工艺下实现,其时钟频率为135Mhz,功耗为52mW,面积约为128．2KGates,峰值处理性能达到6．6GOPs．     

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

一种可重构体系结构用于高速实现DES、3DES和AES

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景.然而目前的可重构密码芯片吞吐率均大大低于专用芯片,因此,如何提高处理速度是可重构密码芯片设计的关键问题.本文分析了常用对称密码算法DES、3DES和AES的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构.基于该体系结构实现的DES、3DES和AES吞吐率在110MHz工作频率下分别可达到7Gbps、2.3Gbps和1.4Gbps.与其他同类设计相比,本文设计在处理速度上有较大优势,可以很好地应用到可重构密码芯片设计中.     

“数字工频陷波器”实验设计

学生普遍反映数字信号处理课程公式繁多,所开设实验脱离工程实践。针对此问题,设计了“数字工频陷波器”实验。基于学生已学课程,综合运用Multisim、MATLAB等软件工具作辅助开发,使用运算放大器、单片机等器件完成本实验。实验方案具有多样性,针对不同的学生,实验参数容易调整。实践表明,本实验可使学生提高对本课程的兴趣,加深对理论知识的理解程度,提高学生对知识的综合运用能力和动手能力。     

一种基于DSP和FPGA的图像处理系统

设计了一种以FPGA为数据采集逻辑控制单元,以DSP为高端图像处理单元的数字图像处理系统。介绍了该系统的硬件组成、工作原理。从视频编码单元、图像处理单元和视频输出单元对整个系统的构成和设计进行了描述,分析了系统设计时的各个关键技术环节。     

一款应用于多模式无线发射机的65nm可配置低功耗滤波器

针对多模式(GSM/TD-SCDMA/WCDMA)无线发射机设计了一款可配置的4阶有源RC低通滤波器.滤波器的截止频率通过数字配置运放外围的无源器件进行改变,从而满足不同模式的带宽要求;同时,滤波器中运放的增益带宽积(GBW)也进行相应的配置,实现滤波器的低功耗设计.针对后者,对滤波器中运放的增益带宽积对滤波器的传递函...     

LS-DSP中串行分布式数字滤波器的功耗优化设计

采用一种优化阶符的二进制数据表示方法,达到了减小LS-DSP内串行分布式计算滤波器的动态功耗的目的．实验结果表明,该方法可有效减小LS-DSP内串行分布式计算滤波器10%的动态功耗．