Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm³. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.     

Wafer-level hermetic MEMS packaging by anodic bonding and its reliability issues

This paper reviews wafer-level hermetic packaging technology using anodic bonding from several reliability points of view. First, reliability risk factors of high temperature, high voltage and electrochemical O₂ generation during anodic bonding are discussed. Next, electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed. The reliability of both hermetic sealing and electrical feedthrough must be simultaneously satisfied. In the last part of this paper, a new wafer-level MEMS packaging material, anodically-bondable low temperature cofired ceramic (LTCC) wafer, is introduced, and its reliability data on hermetic sealing, electrical interconnection and flip-chip mounting on a printed circuit board (PCB) are described.     

基于LTCC技术的无源器件设计方法

作为一种新型的集成封装技术,低温共烧陶瓷（LTCC）技术以其优良的高频和高速传输特性,小型化、高可靠性而备受关注。由此可见研究如何利用LTCC技术开发高性能的小型化无源器件对于无线通信产品的发展是有实际意义的。LTCC技术能充分利用三维空间发展多层基板技术,其产品在封装和小型化方面具有明显优势;LTCC技术具有损耗小、高频性能稳定、温度特性良好等特点。同时介绍了国内外LTCC元器件发展现状和趋势,以及基于LTCC技术的无源器件的设计和应用。     

用于制造微波多芯片组件的LTCC技术

低温共烧陶瓷(LTCC)是实现微波多芯片组件(MMCM)的一种理想的组装技术,具有高集成密度、多种电路功能和高可靠性等技术优势.介绍了国内外应用于微波组件的LTCC技术发展现状,概述了LTCC的制造工艺流程,分析了其关键工艺难点,对LTCC基板电路的设计进行了详细阐述,并讨论了埋层电阻的设计和微带线和带状线间的垂直微波互联的方式.利用LTCC技术研制的微波多芯片组件,在现代雷达和通讯领域具有广泛的应用前景.     

一种应用于电子封装的热匹配工艺设计

作为组件封装材料,铝合金与芯片和电路基板之间存在热膨胀不匹配问题.采用热匹配工艺设计,选择合适的热匹配材料,为铝合金盒体与LTCC基板热膨胀匹配提供了一种理想解决方案.根据匹配设计理念,利用Abaqus有限元软件对热匹配材料及铝盒体的结构进行了仿真和优化,并与加工出试验样品的测试结果进行了对比,验证了模拟结果,为铝合金...     

基于LTCC技术的表贴式封装SAWF

提出一种基于低温共烧结陶瓷(LTCC)技术的封装形式,将声表面波滤波器(SAWF)做成表面贴装器件(SMD).该封装结构可实现SAWF基片表面上方2个换能器间的隔离,提高SAWF的阻带抑制,其器件适合于高密度组装,进而可演变成SAWF集成在电路模块的LTCC多层电路板上,即直接将SAWF的裸基片掩埋在LTCC多层电路板内,实现器件—电路—体化.     

Integrated Systems [systems on a chip]

Integrated Systems are defined as batch-fabricated interconnections of complex digital integrated circuits with analog interface circuits and transducers, such as sensors. By providing the cost, performance and reliability levels of monolithic integration, they offer potential advantages over multi-chip modules assembled with packaging technology. This paper studies the required process technology, as well as design, test and packaging issues, for integrating wide varieties of systems. The goal is to delineate the necessary steps in bringing Integrated Systems to market within a realistic period. With monolithic integration as the ultimate aim, a multi-chip entry point is identified that can start system technology on a learning curve of cost reduction using the same scaling principles that drive integrated circuits. Three challenges to be surmounted are identified in streamlining the I/O's and progressing along a learning curve, namely I/O scaling, I/O loading, and full-functional test. The “composite IC” is the entry point. A large chip, containing only global interconnects and power distribution, acts as a silicon backplane. Subsystem-chips, such as digital microprocessors or sensors, are flip-chip mounted using the accuracy of MEMS processing to fabricate “snap-together” physical and electrical interfaces with high reproducibility. While similar to conventional MCM's, this chip-to-chip connection has few compromises over on-chip connections. By keeping the fabrication responsibility within one organization, just as in monolithic chips, there is no need for incoming inspection. Added ESD protection and test-head loading are avoided on interior nodes by a new intra-factory method of testing     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。     

基于LTCC技术的三维集成微波组件

低温共烧陶瓷(LTCC)技术和三维立体组装技术是实现微波组件小型化、轻量化、高性能和高可靠的有效手段.本文研究实现了基于LTCC技术的三维集成微波组件,对三维集成微波组件的立体互连结构、三维集成LTCC微波电路的垂直微波互连、微波多芯片模块(MMCM)的垂直微波互连等关键技术进行了重点阐述.研制出的三维集成微波组件的体积和重量分别比传统的二维平面LTCC集成微波组件减小40%和38%,电气性能相当.     

应用于柔性电子的超薄硅基芯片研究进展北大核心

柔性电子技术在近些年得到了快速发展，越来越多的柔性电子系统需要柔性、高性能的集成电路来实现数据处理和通信。通过减薄硅基芯片可以获得高性能的柔性集成电路，但是硅基芯片减薄之后的性能有可能发生变化，并且在制备、转移、封装的过程中极易产生缺陷或者破碎，导致芯片性能退化甚至失效。因此，超薄硅基芯片的制备工艺和柔性封装技术对于制备高可靠性的柔性硅基芯片十分关键。在此背景下，文章综述了柔性硅基芯片的力学和电学特性研究进展，介绍了几种超薄硅基芯片的减薄工艺和柔性封装前沿技术，并对超薄硅基芯片在柔性电子领域的应用和发展进行了总结和展望，为柔性硅基芯片技术的进一步研究提供参考。     

复合双性LTCC材料基础研究

随着电子技术在自动化、工业控制、医学、航天航空和日常生活等领域的广泛应用,高密度、宽温域、小尺寸、多功能、高品质等特性日益成为其发展的必然趋势,同时这些特性给传统封装技术及工艺带来了巨大的挑战。在众多的封装技术中,低温共烧陶瓷LTCC(Low Temperature Co-fired Ceramic)技术成为了国际研究的焦点,因为利用LTCC技术制备的产品不仅能具备高电流密度、小体积,而且还具备高可靠性和优良的电性能、传输特性及密封性。LTCC技术是一种先进的混合电路封装技术。它将四大无源器件,即变压器(T)、电容器(C)、电感器(L)和电阻器(R)集成,配置于多层布线基板中,与有源器件(如:功率MOS、晶体管和IC电路模块等)共同集成为一完整的电路系统。因此LTCC技术又称为混合集成技术,它能有效地提高电路的封装密度及系统的可靠性。笔者围绕LTCC技术中的低温共烧铁氧体LTCF(Low Temperature Co-fired Ferrite)材料,采用理论、实验及应用三位一体的研究模式,开发了一种新型LTCC复合介质材料,不但对该材料的复合机理进行了理论模拟而且对其在LTCC滤波器中的应用展开了研究。笔者在理论模型、材料制备和器件设计上做了一些探索性和创新性的工作,具体内容如下:(1)探索性地建立了针对LTCC陶瓷的低温烧结模型。模型基于液相烧结理论,以液相在晶粒边界引起的毛细管压力及溶解–淀析过程中化学势能的变化为烧结驱动力,将烧结温度、时间与烧结后的最终晶粒大小、相对密度联系起来,模拟出低温烧结动态过程中相对密度的变化趋势。(2)首次提出铁电–铁磁复合材料的复合理论并给予了系统的分析。讨论了复合材料中两相成分的化学结构及电磁性能在理论上对复合可能性的影响,根据材料的微观结构建立了复合模型,模型中假设铁电相均匀分布于铁磁相晶粒表面,并和气孔一起形成非磁性薄层将铁磁晶粒之间隔断,使铁磁颗粒孤立。通过对复合结构中铁磁晶粒内场变化的分析,推导出复合材料铁电/铁磁成分比与复合磁导率的关系方程;另外,利用微观结构中电流流通的等效电路,推导得到不同铁电/铁磁成分比时复合材料复数介电常数与频率的关系表达式。(3)研究了工艺条件对材料电磁性能的影响。按照工艺流程改变工艺参数预烧温度、二次球磨时间、烧结曲线中升温降温速度、烧结温度和保温时间,通过SEM、XRD等分析手段了解改变工艺参数对铁氧体材料微观结构的影响规律,通过对材料介电常数频谱、磁导率频谱及品质因数的测量得知工艺参数对材料电磁性能的影响规律,根据实验数据结果得到最佳铁氧体烧结工艺参数。(4)研究了不同掺杂离子及助熔剂的加入对低温烧结铁氧体LTCF材料的微观结构及电磁性能影响。首先研究了不同MnCO3和CuO含量对NiZn铁氧体烧结特性、微观结构及电磁性能的影响,首次发现了掺杂Mn离子的NiZn铁氧体其电磁性能对烧结温度具有敏感性。其次研究了不同助熔剂Bi2O3、WO3和Nb2O5对NiCuZn铁氧体烧结特性、微观结构及电磁性能的影响,实验揭示W6+对材料微观结构的改善;最后对低温NiCuZn铁氧体进行改性掺杂,研究稀土氧化物CeO2对其微观结构及电磁性能的影响,并给出NiCuZn铁氧体掺杂稀土元素时的磁频谱及介频谱。(5)开发了一新型的基于不同低温烧结NiCuZn铁氧体与高介电常数(BaTiOk+X)钙钛矿的具有电感、电容双性的铁电–铁磁复合材料,研究了不同铁电–铁磁含量对各组复合材料微观结构及电容电感双性的影响。并研究了不同助熔剂Bi2O3、WO3和Nb2O5对其烧结特性、微观结构及电容电感双性的影响。最后对复合材料进行稀土掺杂改性,研究稀土氧化物CeO2对其微观结构及电容电感双性的影响。(6)设计并制作出两种使用LTCC复合双性材料的3G通讯设备用带通滤波器。采用Ansoft HFSS电磁仿真软件对所建立的滤波器模型进行模拟仿真,通过调节滤波器结构参数使滤波器各性能指标达到要求,并实现生产制备。制得带通中心频率3.5 GHz,插损<2.8 dB,带宽>400 MHz,阻带衰减大于35 dB的微带式带通滤波器和带通中心频率1.4 GHz,插损<3 dB,带宽>160 MHz,阻带衰减大于30 dB的LC式带通滤波器。     

LTCC基板金丝热超声楔焊正交试验分析

引线键合是微组装技术中的关键工艺,广泛应用于军品和民品芯片的封装。特殊类型基板的引线键合失效问题是键合工艺研究的重要方向。低温共烧陶瓷(LTCC)电路基板在微波多芯片组件中使用广泛,相对于电镀纯金基板,该基板上金焊盘楔形键合强度对于参数设置非常敏感。文章进行了LTCC基板上金丝热超声楔焊的正交试验,在热台温度、劈刀安装长度等条件不变的情况下,分别设置第一键合点和第二键合点的超声功率、超声时间和键合力三因素水平,试验结果表明第一点超声功率和第二点超声时间对键合强度影响明显。     

Characterization and performance prediction for integral capacitorsin low temperature co-fired ceramic technology

This paper addresses the electrical characterization of integral capacitors in low temperature co-fired ceramic (LTCC). The technology also includes integrated resistors and inductors. It first discusses the geometry and fabrication of the capacitor technology, which uses a novel insert method in LTCC substrates. The structures of 300 special test vehicles made to analyze the technique are described. The samples include components in the range 140 pF to 9.6 nF, and single-layer and two-layer integral formats; structure fabrication capability is currently 7.8 nF/cm². Test vehicle variants, fabricated to analyze the effects of processing parameters such as lamination pressure, are discussed. Measurement systems, which were built to electrically characterize the integral capacitors, are described. The results of the analyzes are summarized with regard to the individual and combined impact of applied frequency, temperature, and DC voltage parameters. The effects of lamination pressure, capacitor size, and the number of dielectric layers are also evaluated. The paper then discusses the development of predictive functions for the induced electrical performance variations in the capacitors, functions that are necessary to enable designers to properly develop circuits for applications in various operating environments. The results of an analysis of the geometry of the capacitors are presented, and are employed by electrical models made using analytical methods, boundary element methods (BEM), and finite element methods (FEM). The models are a requirement for process engineers in optimizing the capacitor fabrication techniques, and for design engineers as means of defining the correct component geometries for their circuits     

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the I_ON current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.     

集成电力电子模块封装的关键技术

封装技术直接影响到集成电力电子模块(Integrated Power Electronics Module,IPEM)的电气性能、EMI特性和热性能等,被公认为未来电力电子技术发展的核心推动力。介绍了IPEM封装的结构与互连和基板技术等关键技术及研究现状,分析了已存在的薄膜覆盖封装技术等三维IPEM封装技术,讨论了IPEM封装的发展趋势,最后指出我国IPEM封装技术研究的限制因素与对策。     

Properties of laser cut LTCC heaters

This article describes fabrication and properties of buried microheaters made inside low temperature co-fired ceramics (LTCC) structures. Laser cutting is used for meander pattern generation in dried Pt, PtAu or PdAg conductive pads. The electrical characterisation of microheaters is based on measurement and analysis of R(T) dependence in the range from 20°C to 850°C, measurement and analysis of thermal dynamic properties, long-term high-temperature passive or active ageing and behaviour of the heater in a pulse operation mode. The presented results are very promising for application of LTCC microheaters in various microsystem devices.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Chip-level vacuum packaging of micromachines using NanoGetters

A new approach to vacuum packaging of micro-machined resonant, tunneling, and display devices is covered in this paper. A multi-layer, thin-film getter, called a NanoGetter, which is particle free and does not increase the chip size of the microsystem has been developed and integrated into conventional wafer-to-wafer bonding processes. Hermetic electrical feedthroughs are also provided as part of this total-solution technology. Experimental data taken with silicon resonators is presented in which Q values in excess of 21,000 have been obtained. Applications for this technology include gyroscopes, accelerometers, displays, flow sensors, density meters, infrared (IR) sensors, microvacuum tubes, radio frequency microelectromechanical systems (RF-MEMS) and pressure sensors.     

Modular, device-scale, direct-chip-attach packaging formicrosystems

A pressing challenge to the commercial implementation of prototype microsystems is the reduction of package size and cost. To decrease package size, a process was developed for the fabrication of high-aspect-ratio, through-wafer interconnect structures. These interconnects permit device-scale packaging of microsystems and are compatible with modern surface mount technology such as flip chip assembly. To minimize package cost, a modular wafer-level silicon packaging architecture was devised. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications     

低温共烧陶瓷技术现状与趋势

综述了低温共烧陶瓷技术进展现状与应用市场前景,指出了集成电路封测产业在进入后摩尔时期面对高密度组装的挑战中,应对多层布线集成封装中LTCC技术的发展趋势。