Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Sidewall defects of AlGaN/GaN HEMTs evaluated by low frequency noise analysis

The traditional dry etching isolation process in AlGaN/GaN HEMTs causes the gate metal to contact the mesa sidewalls region, forming a parasitic gate leakage path. In this paper, we suppress the gate leakage current from the mesa-sidewall to increase the gate-to-drain breakdown voltage and thereby reduce the interface trap density by using the ion implantation (I/I) isolation technology. According to the capacitance–voltage (C–V) measured curve, the hysteresis voltage was 9.3 mV and the interface state density was 5.26 × 10¹² cm⁻² for the I/I isolation sample. The 1/f noise phenomena and Schottky characteristics are particularly studied to indicate device linearity, which is sensitive to the semiconductor surface. The fluctuation that causes trapping/detrapping of free carriers near the gate interface can be reduced because side-wall plasma-induced damages were eliminated. The reduced DC and flicker noise variation of I/I isolation HEMTs is beneficial for high power transistor applications.     

Theoretical and practical investigation of the thermal generation in gate controlled diodes

The different components of thermal generation in a gate controlled diode are studied theoretically and experimentally. Expressions for the generation current in the space charge layer, the diffusion current from the quasi-neutral bulk and the surface generation current are derived for a gated-diode. The width of the generation zone within the space charge layer is calculated as a function of the energy level of the trap and the diode reverse voltage. This leads to a characteristic of the leakage current as a function of the space charge layer width. It is pointed out that the diffusion current can influence the leakage current and cannot be neglected in structures with a low dark current. In the second part the gate controlled diode is used to characterize the thermal generation in structures with a homogeneous and low dark current. A generation lifetime of 5.5 msec and a surface generation velocity at a depleted surface of 1.5 cm/sec is derived. The generation lifetime is found to be constant as a function of depth into the substrate. A considerable diffusion current is measured which is comparable to the generation current in the space charge layer.     

Highly robust ultrathin silicon nitride films grown atlow-temperature by microwave-excitation high-density plasma for gigascale integration

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400°C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

AlGaN/GaN HEMT device reliability and degradation evolution: Importance of diffusion processes

A methodology based on combined electrical trapping analysis with UV-assisted preparation of trap states and electroluminescence analysis was developed to gain detailed understanding of trap generation in AlGaN/GaN HEMTs during off and on-state stress. This is used to identify electronic trap location laterally and vertically in a device structure and the nature of the degradation mechanism. We identify the generation of traps with activation energies in the range from 0.45 to 0.65 eV near the gate edge on its drain side in AlGaN/GaN HEMTs as electronic traps in the AlGaN device layer, as a result of on- and off-state stress. Degradation studied on devices subjected to stress under different backplate temperatures, points to diffusion processes playing an important role for early device degradation. Diffusion constants showed thermal activation energies of ∼0.26 eV consistent with diffusion processes along dislocations, with possible additional contributions from bulk diffusion accelerated by converse/inverse piezo-electric strain and leakage currents.     

碳掺杂对28 nm PMOS器件性能的影响

基于28 nm Polysion工艺,研究了在轻掺杂源漏区(LDD)提升掺杂浓度与掺杂碳源对PMOS器件的影响。实验结果表明,掺杂碳原子可以有效抑制硼的瞬时增强扩散效应(TED),并有效降低器件结深,降低漏电流。在P型轻掺杂源漏区(PLDD)提升掺杂浓度,可以有效提高电路速度,但会导致更严重的硼扩散与漏电流。通过研究不同浓度的碳原子与PLDD浓度对器件的影响,选取合适的碳源掺杂浓度并提高PLDD的掺杂浓度,在同样饱和电流的情况下器件具有更小的漏电流,可以提升PMOS器件的饱和电流与漏电流(I_on-I_off)性能约6%。     

Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gateoxide with excellent performances in reduction of leakage current andboron diffusion

Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation     

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO₂ gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (V_O − O_i) – could consistently explain the experimental observations. An interesting feature of the V_O − O_i defect is that it can exists in various metastable configurations with the interstitial oxygen O_i in different positions around the vacancy V_O, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.     

Decaborane (B10H14) ion implantationtechnology for sub-0.1-μm PMOSFET's

A low-energy, high-dosage boron ion implantation technology using a decaborane (B₁₀H₁₄) molecule is developed. Since B₁₀N₁₄ consists of ten boron atoms, they are implanted with about a one-tenth lower effective acceleration energy and ten times higher effective beam current compared with those of boron. We demonstrated an ultrashallow boron profile with 0.5 keV effective acceleration energy, which does not cause transient enhanced diffusion (TED) after rapid thermal annealing (RTA). Using this technology, we succeeded in fabricating 0.1-μm PMOSFET's with good device performances and excellent suppression of short-channel effects     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

Design and development of two-dimensional position sensitive photo-detector

Position sensitive photo-detectors (PSDs) utilize the lateral photovoltaic effect to produce an electrical output that varies linearly with the position of a light spot incident on a semiconductor junction. Design, fabrication and characterization of newly developed silicon PSD, which employ the planar technology and double ion implantation with different doses, are described. Shallow and low-doped p-n junction is formed by boron implantation in n-type silicon substrate. The position characteristics of PSD are symmetric to the zero and linear in the 80% of the active area. For a higher resistivity top layer (lower implanted dose), the sensitivity grows up and the linearity gets improved. The influence of the substrate is not substantial for the position characteristics. The response of the sensor, measured by pulsed 15 ns laser, was determined to be about 100 ns. Described PSD has been used in the construction of simple light spot rotational follower.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Carrier transport mechanism in La-incorporated high-k dielectric/metal gate stack MOSFETs

In this paper, carrier transport mechanism of MOSFETs with HfLaSiON was analyzed. It was shown that gate current is consisted of Schottky emission, Frenkel-Poole (F-P) emission and Fowler-Nordheim (F-N) tunneling components. Schottky barrier height is calculated to be 0.829 eV from Schottky emission model. Fowler-Nordheim tunneling barrier height was 0.941 eV at high electric field regions and the trap energy level extracted using Frenkel-Poole emission model was 0.907 eV. From the deviation of weak temperature dependence for gate leakage current at low electric field region, TAT mechanism is also considered.     

Characterization of the effectiveness of carbon incorporation inSiGe for the elimination of parasitic energy barriers in SiGe HBTs

An electrical method is applied to SiGe and SiGe:C heterojunction bipolar transistors (HBTs) to extract the bandgap narrowing in the base layer and to characterize the presence of parasitic energy barriers in the conduction band, arising from boron transient enhanced out-diffusion from the SiGe layer. It is shown that a background carbon concentration within the base (≈10²⁰ cm^-3) eliminates parasitic energy barriers at the collector/base junction, and hence shows that transient enhanced diffusion of boron from the base has been completely suppressed     

Thermal and Electrical Properties of PVD Ru(P) Film as Cu Diffusion Barrier

Thermal and electrical properties of physical vapor deposition (PVD) Ru(P) film deposited on porous ultra low-k (p-ULK) material as Cu diffusion barrier were studied. The phosphorous concentration can be tuned by adjusting Ar to PH₃ ratio of the sputtering gases. The leakage current depends on phosphorous concentration. Higher phosphorous content in Ru film has lower leakage current. No obvious phosphorous content dependence was observed when the amorphous Ru(P) film crystallized. The X-ray diffraction (XRD) graphs and energy dispersive spectrometer’s (EDS) atomic depth profiles show that the Ru(P) film deposited on p-ULK can effectively block Cu diffusion when the sample is subjected to 800 °C 5 min annealing. The phosphorous doped Ru film improves diffusion barrier properties and leakage current performance. The improved Ru(P) barrier capable of direct Cu plating could be a potential candidate for advanced metallization.     

The influence of assisted ion beam bombardment on structure and electrical characteristics of HfSiO dielectric synthesized by DIBSD

We have investigated the influence of assisted ion beam bombardment on structure and electrical properties of HfSiO dielectrics deposited on Si (1 0 0) substrate by dual-ion beam sputtering deposition (DIBSD). The X-ray photoelectron spectroscopy (XPS) analysis indicates that assisted ion beam bombardment could suppress the formation of Si clusters and partial SiO bonds. The excellent electrical properties with maximum dielectric constant (18.6) and the smaller oxide-charge density (7.2 × 10¹¹ cm⁻²) and leakage current (2.8 × 10⁻⁷ A/cm² at (V_fb−1) V) were obtained for HfSiO film by assisted ion beam bombardment at AIE = 100 eV, which provide a initial energy for the formation of film, activate the substrate surface atoms, enhance the polarization rate and improve the film surface compact and adhesion.     

Very shallow boron junctions in Si by implantation and SOD diffusion obtained by RTP

Because of their very large integration capabilities and continuous scaling, the CMOS devices are the basic element in the current-integrated circuits. Their scaling up to sub-micrometric scale presents advantages like diminution of power consumption, faster devices and a larger level of integration. But the physics limitations begin to be important at these dimensions, anomalous effects like hot electrons, leakage currents and punch through, among others, appear. These effects can be reduced if, at the source/drain region, shallow junctions are obtained with junction depth (x_j) less than 200 nm. To achieve this goal, new junction fabrication methods, which include pre-amorphization [S.D. Kim, C.M. Park, J.C.S. Woo, Formation and control of box-shaped ultra-shallow junction using laser annealing and pre-amorphization implantation, Solid State Electron. 49 (2005) 131–135] are required. Other alternative techniques that do not require ion implantation [T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba, A CMOS-compatible rapid vapor-phase doping process for CMOS scaling, IEEE Trans. Electron Devices 51(1) (2004) 14–19.], in order to prevent surface crystal damage and as a consequence the inhibition of boron interstitial clusters and {3 1 1} defects [R.T. Crosby, K.S. Jones, M.E. Law, L. Radic, Dislocation loops in silicon–germanium alloys: the source of interstitials, Appl. Phys. Lett. 87 (192111) (2005) 1–3.], which are the trigger of the “transient enhanced diffusion” (TED) process are used. In this essay, it is shown that rapid thermal process, allow the fabrication of very shallow junctions with a x_j less than 300 nm by using with high energies and high doses of boron/BF₂ ions implantation. By this way the slow dissolution of the dislocation loops, present at the end of range (EOR) of the implanted boron, allow this process. These obtained junctions are compared with those prepared by using the spin on doping (SOD) technique. The diffusion profiles obtained by both processes and their electrical properties are measured and compared for their application as S–D regions in a current CMOS process.     

Gapless point back surface field for the counter doping of large‐area interdigitated back contact solar cells using a blanket shadow mask implantation process

Gapless interdigitated back contact (IBC) solar cells were fabricated with phosphorous back surface field on a boron emitter, using an ion implantation process. Boron emitter (boron ion implantation) is counter doped by the phosphorus back surface field (BSF) (phosphorus ion implantation) without gap. The gapless process step between the emitter and BSF was compared to existing IBC solar cell with gaps between emitters and BSFs obtained using diffusion processes. We optimized the doping process in the phosphorous BSF and boron emitter region, and the implied V_oc and contact resistance relationship of the phosphorous and boron implantation dose in the counter doped region was analyzed. We confirmed the shunt resistance of the gapless IBC solar cells and the possibility of shunt behavior in gapless IBC solar cells. The highly doped counter doped BSF led to a controlled junction breakdown at high reverse bias voltages of around 7.5 V. After the doping region was optimized with the counter doped BSF and emitter, a large‐area (5 inch pseudo square) gapless IBC solar cell with a power conversion efficiency of 22.9% was made.