Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.     

A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations

The impact of parameter variations on timing due to process variations has become significant in recent years. In this paper, we present a statistical timing analysis (STA) framework with quadratic gate delay models that also captures spatial correlations. Our technique does not make any assumption about the distribution of the parameter variations, gate delays, and arrival times. We propose a Taylor-series expansion-based quadratic representation of gate delays and arrival times which are able to effectively capture the nonlinear dependencies that arise due to increasing parameter variations. In order to reduce the computational complexity introduced due to quadratic modeling during STA, we also propose an efficient linear modeling driven quadratic STA scheme. We ran two sets of experiments assuming the global parameters to have uniform and Gaussian distributions, respectively. On an average, the quadratic STA scheme had 20.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.00135 units between the two timing cummulative density functions (CDFs). The linear modeling driven quadratic STA scheme had 51.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.0015 units between the two CDFs. Our proposed technique is generic and can be applied to arbitrary variations in the underlying parameters under any spatial correlation model     

Statistical modeling of reliability in logic devices

Due to continuous technology scaling VLSI circuits feature an increasing susceptibility to transient faults. While complete elimination of errors cannot be guaranteed, current mitigation techniques based on circuit improvement or architectural measures cause a large overhead in terms of area and energy consumption. A more efficient possibility to cope with transient faults can be to tolerate hardware errors at low physical levels and handle them at higher system levels. This can be achieved by reusing error handling capabilities – such as channel decoders – or introducing specialized error correction blocks that take advantage of the system characteristics by concentrating the effort on the components and bits most crucial for system operation. To enable this approach the influence of hardware errors on system performance needs to be evaluated, requiring spatial and temporal models of error propagation in the system. Since Monte Carlo simulation of complex systems is not feasible, a statistical modeling technique of logic gates and circuits is introduced. This approach allows modeling of noise and variability influences on logic gates as well as correlation due to reconvergent fan-out with an error of 5% compared to Monte Carlo simulation but with considerably less runtime.     

Development of robust interconnect model based on design ofexperiments and multiobjective optimization

When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 μm CMOS technology; optimization results are discussed and verified using Monte Carlo simulation     

Statistical device models from worst case files and electrical testdata

Two statistical metal oxide semiconductors (MOS) models are described, one based on worst case files and the other on electrical test data. The former is appropriate for predicting the variability of a process early in its life cycle, while the latter would better track a maturing process. The key statistical tool that is used to develop the models is principal component analysis (PCA), which is used in novel ways in order to derive statistical models from readily available information. The models are used to perform statistical circuit simulation in order to quantitatively predict the impact of manufacturing variations on circuit performance metrics. Due to the use of linear response surface modeling and latin hypercube sampling, the simulation cost of using the models is about the same as with worst case simulation. The modeling technique is general and is applicable to other semiconductor devices besides MOS devices which are considered in this paper     

Process variation-aware performance analysis of asynchronous circuits

Current technology trends have led to the growing impact of process variations on performance of asynchronous circuits. As it is imperative to model process parameter variations for sub-100nm technologies to produce a more real performance metric, it is equally important to consider the correlation of these variations to increase the accuracy of the performance computation. In this paper, we present an efficient method for performance evaluation of asynchronous circuits considering inter- and intra-die process variation. The proposed method includes both statistical static timing analysis (SSTA) and statistical Timed Petri-Net based simulation. Template-based asynchronous circuit has been modeled using Variant-Timed Petri-Net. Based on this model, the proposed SSTA calculates the probability density function of the delay of global critical cycle. The efficiency for the proposed SSTA is obtained from a technique that is derived from the principal component analysis (PCA) method. This technique simplifies the computation of mean, variance and covariance values of a set of correlated random variables. In order to consider spatial correlation in the Petri-Net based simulation, we also include a correlation coefficient to the proposed Variant-Timed Petri-Net which is obtained from partitioning the circuit. We also present a simulation tool of Variant-Timed Petri-Net and the results of the experiments are compared with Monte Carlo simulation-based method.     

Characterization of Standard Cells for Intra-Cell Mismatch Variations

With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider intra-cell process mismatch variations to characterize a cell's delay and output transition time (output slew) variations. A straightforward approach to address this problem is to model these mismatch variations by characterizing for each device fluctuation separately. However, the runtime complexity for such characterization becomes of the order of number of devices in the cell and the number of simulations required can easily become infeasible. We analyze the fluctuations in switching and nonswitching devices and their impact on delay variations. Using these properties of the devices, we propose a clustering approach to characterize for cell's delay variations due to intra-cell mismatch variations. The proposed approach results in as much as 12X runtime improvement with acceptable accuracy, compared with Monte Carlo simulation. We show that this approach ensures an upper bound on the results while keeping the number of simulations for each cell independent of the number of devices.      

Statistical analysis of subthreshold leakage current for VLSI circuits

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.     

Circuit sensitivity to interconnect variation

Deep submicron technology makes interconnect one of the main factors determining the circuit performance. Previous work shows that interconnect parameters exhibit a significant amount of spatial variation. In this work, we develop approaches to study the influence of the interconnect variation on circuit performance and to evaluate the circuit sensitivity to interconnect parameters. First, an accurate interconnect modeling technique is presented, and an interconnect model library is developed. Then, we explore an approach using parameterized interconnect models to study circuit sensitivity via a ring oscillator circuit. Finally, we present an alternative approach using statistical experimental design techniques to study the sensitivity of a large and complicated circuit to interconnect variations     

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique

With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.     

Monte Carlo optimization of superconducting complementary outputswitching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix     

Statistically based parametric yield prediction for integratedcircuits

This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: (1) a multivariate nested model is used to reproduce random process-induced device-variations, rather than the multivariate multinormal model typically used, and (2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++     

Accounting for variability in the design of circuits with organic thin-film transistors

We experimentally verify that the methodology to account for local parameter variations and transistor mismatch known in Si CMOS technologies can be transposed to organic thin-film transistor technologies, and we present a design case that makes use of design for variability. Transistor parameter variation decreases with the square root of the transistor footprint. As a consequence, Monte Carlo simulations which take this effect into account can be executed to better predict the final circuit yield. The design case in this work is an 8-bit, organic RFID transponder chip. The yield prediction by simulations corresponds to the finally observed circuit yield.     

A low-phase noise injection-locked quadrature voltage-controlled oscillator

This article presents a low-phase noise quadrature voltage-controlled oscillator (QVCO) in which the re-filtering technique of the side-band noise is adopted. In the proposed QVCO, besides using re-filtering technique, the passive elements replaced the noisy and lossy active coupling devices. Therefore, due to the elimination of the associate noise sources of the active coupling devices and re-filtering of side-band noise of the circuit, the proposed QVCO shows an excellent phase-noise and FOM. The proposed QVCO was implemented and simulated in TSMC 0.18 μm RF-CMOS technology. The phase noise of the proposed QVCO at 3 MHz offset frequency from the 3 GHz center frequency is ?144 dBc/Hz, for a current consumption of 11.5 mA at a power supply of 1.8-V. Simulation results show the proposed QVCO can operate with power supply as low as 0.6 V. Monte–Carlo analyses for, 3% device mismatch and process variation, result in phase error lower than 0.8°. Generalizing the proposed coupling technique to several core VCOs very low-phase noise multiphase signals can be generated.     

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.     

An autoregressive model for analysis of ice sheet elevation change time series

We present an autoregressive (AR) model that can effectively characterize both seasonal and interannual variations in ice sheet elevation change time series constructed from satellite radar or laser altimeter data. The AR model can be used in conjunction with weighted least squares regression to accurately estimate any longer term linear trend present in the cyclically varying elevation change time series. This approach is robust in that it can account for seasonal and interannual elevation change variations, missing points in the time series, signal aperiodicity, time series heteroscedasticity, and time series with a noninteger number of yearly cycles. In addition, we derive a theoretically valid estimate of the uncertainty (standard error) in the long-term linear trend. Monte Carlo simulations were conducted that closely emulated actual characteristics of five-year elevation change time series from Antarctica. The Monte Carlo results indicate that the autoregressive approach yields long-term linear trends that are less biased than two other approaches that have been recently used for analysis of ice sheet elevation change time series. In addition, the simulation results demonstrate that the variability (uncertainty) of the long-term linear trend estimates from the AR approach is in very good agreement with the derived theoretical standard error estimates.     

Statistical BSIM model for MOSFET 1/f noise

A statistical model for MOSFET 1/f noise implemented as an extension to BSIM and integrated into a process design kit is presented. Excellent model to hardware correlation is shown on measured noise statistics from over 200 devices. The statistical model enables circuit designers to run Monte Carlo and corner noise simulations, and captures the device area and bias dependence of noise variance.