Electrical characterisation of SiON/n-Si structures for MOS VLSI electronics

In the present work, we examine the properties of SiON films grown on Si substrates by CVD in order to investigate their suitability as potential materials in replacing SiO₂ in metal-oxide-semiconductor (MOS) devices. Suitable metallization created MOS devices and electrical characterisation took place in order to identify their electrical properties. Electrical measurements included current-voltage (I-V), capacitance-conductance-voltage (C-V) measurements and admittance spectroscopy (Y−ω) allowing determination of the bulk charges and the dielectric response of the films. The analysis of the data also took into account the presence of traps at the Si/SiON interface calculated by a fast conductance technique. The interface states density was of the order of 10¹² eV⁻¹ cm⁻². The dielectric constant was found to lie between 16 and 4.5 and the corresponding bulk trapped charges were found between 8 and 113 μCb cm⁻². Post deposition annealing altered these values showing an improvement of the device behaviour. A short explanation of the above is also provided.     

Electrical analysis of organic dye-based MIS Schottky contacts

In this work, we prepared metal/interlayer/semiconductor (MIS) diodes by coating of an organic film on p-Si substrate. Metal(Al)/interlayer(Orange GOG)/semiconductor(p-Si) MIS structure had a good rectifying behavior. By using the forward-bias I-V characteristics, the values of ideality factor (n) and barrier height (BH) for the Al/OG/p-Si MIS diode were obtained as 1.73 and 0.77 eV, respectively. It was seen that the BH value of 0.77 eV calculated for the Al/OG/p-Si MIS diode was significantly larger than the value of 0.50 eV of conventional Al/p-Si Schottky diodes. Modification of the potential barrier of Al/p-Si diode was achieved by using thin interlayer of the OG organic material. This was attributed to the fact that the OG organic interlayer increased the effective barrier height by influencing the space charge region of Si. The interface-state density of the MIS diode was found to vary from 2.79 × 10¹³ to 5.80 × 10¹² eV⁻¹ cm⁻².     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Modulation of surface solubility and wettability for high-performance inkjet-printed organic transistors

The surface solubility and wettability of photosensitive layers of polystyrene (PS) were engineered to evaluate its effect on the crystalline microstructure and film morphology of inkjet-printed 6,13-bis(triisopropylsiylethynyl) pentacene (TIPS-pentacene). UV exposure proved to be a simple and effective method for modulating the solubility of PS films with controllable crosslinking. As compared with the untreated PS film, the film morphology of the printed semiconductor on the UV-irradiated crosslinked PS films was significantly optimized. The optimal degree of crosslinking and solubility of the PS film were achieved by UV irradiation at a dose of 0.417 J cm⁻². Field-effect transistors fabricated using well-organized crystals on the optimal crosslinked PS film exhibited a maximum mobility of 0.48 cm² V⁻¹ s⁻¹ and an average value of 0.19 cm² V⁻¹ s⁻¹. The performance is clearly superior to that of devices prepared on a pristine PS film (0.02 cm² V⁻¹ s⁻¹).     

The analysis of I-V characteristics of Schottky diodes by thermionic emission with a Gaussian distribution of barrier height

The current-voltage (I-V) characteristics of Al/p-Si Schottky barrier diode (SBD) with native insulator layer were measured in the temperature range of 178-440 K. The estimated zero-bias barrier height Φ_B0 and the ideality factor n assuming thermionic emission (TE) theory have shown strong temperature dependence. Evaluation of the forward I-V data have revealed an increase of zero-bias barrier height Φ_B0 but the decrease of ideality factor n with the increase in temperature. The experimental and theoretical results of the tunneling current parameter E_o against kT/q were plotted to determine predominant current-transport mechanism. But the experimental results were found to be disagreement with the theoretical results of the pure TE, the thermionic-field emission (TFE) and the field emission (FE) theories. The conventional Richardson plot has exhibited non-linearity below 240 K with the linear portion corresponding to the activation energy of 0.085 eV and Richardson constant (A^*) value of 2.48 × 10⁻⁹ A cm⁻² K⁻² which is much lower than the known value of 32 A cm⁻² K⁻² for holes in p-type Si. Such behaviours were attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution of barrier heights (BHs) due to barrier height inhomogeneities that prevail at interface. Thus, the modified ln(I_o/T²) − q2σo2/2k²T² vs q/kT has plotted. Then A^* was calculated as 38.79 A cm⁻² K⁻² without using the temperature coefficient of the barrier height. This value of the Richardson constant 38.79 A cm⁻² K⁻² is very close to the theoretical value of 32 A K⁻² cm⁻² for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I-V characteristics of the Al/p-Si Schottky barrier diodes with native insulator layer can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights.     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

H-aggregation mode in triple-decker phthalocyaninato-europium semiconductors. Materials design for high-performance air-stable ambipolar organic thin film transistors

Two new tris(phthalocyaninato) europium complexes Eu₂(Pc)[Pc(OPh)₈]₂ (1) and Eu₂[Pc(OPh)₈]₃ (2) [Pc = unsubstituted phthalocyaninate; Pc(OPh)₈ = 2,3,9,10,16,17,23,24-octaphenoxyphthalocyaninate], were designed and synthesized. Introduction of different number of electron-withdrawing phenoxy substituents at the phthalocyanine periphery within the triple-decker complexes not only ensures their good solubility in conventional organic solvents, but more importantly successfully tunes their HOMO and LUMO levels into the range of air-stable ambipolar organic semiconductor required on the basis of electrochemical studies over both 1 and 2, meanwhile fine controlling of aggregation mode (H vs. J) in solution-based film for improving OTFT performance is also achieved. Measurements over the OTFT devices fabricated from these sandwich compounds by a solution-based quasi–Langmuir–Shäfer (QLS) method reveal their ambipolar semiconductor nature associated with suitable HOMO and LUMO energy levels. Due to the H-aggregation mode employed by the heteroleptic triple-decker molecules in the QLS film, excellent performances with the electron and hole mobility in air as high as 0.68 and 0.014 cm² V⁻¹ s⁻¹, respectively, have been revealed for the OTFT devices of heteroleptic triple-decker 1. This represents the best performance so far for solution-processable ambipolar single-component phthalocyanine-based OTFTs obtained under ambient conditions. In good contrast, homoleptic analogue 2 prefers to J-type aggregation and this results in relatively lower electron and hole mobility, around 0.041 and 0.0026 cm² V⁻¹ s⁻¹ in air, respectively, for the devices fabricated. In particular, the performance of the devices fabricated based on 1 was found to remain almost unchanged in terms of both the carrier mobilities and on/off ratio even after being stored under ambient for 4 months.     

Dibenzothiophene-S,S-dioxide based medium-band-gap polymers for efficient bulk heterojunction solar cells

Medium-band-gap polymers based on indacenodithiophene (IDT) and dibenzothiophene-S,S-dioxide (SO) derivatives, PIDT-SO and PIDT-DHTSO, were synthesized via a microwave assisted Stille polycondensation. The polymers have the maximum absorption ∼500 nm, high absorption coefficients above 0.6 × 10⁻² nm⁻¹, and medium band gaps of ∼2.2 eV. Their hole mobilities are around 2 × 10⁻⁴ cm² V⁻¹ s⁻¹ as measured by field effect transistors. The photovoltaic performances of the polymers were investigated on the inverted bulk heterojunction (BHJ) devices of ITO/PFN/PIDT-DHTSO:PC₇₁BM (1:3, w/w)/MoO₃/Al, and a power conversion efficiency (PCE) of 3.81% with an open-circuit voltage (V_oc) of 0.95 V, a short-circuit current (J_sc) of 8.20 mA cm⁻² and a fill factor (FF) of 48% were achieved. Those results indicated that dibenzothiophene-S,S-dioxide derivatives could be an excellent electron-deficient building block for medium-band-gap electron-donor polymers.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Comparison of short and long wavelength absorption electron donor materials in C60-based planar heterojunction organic photovoltaics

Buckminsterfullerene, C₆₀-based planar heterojunction (PHJ) organic photovoltaics (OPVs) have been created using a short wavelength absorption (λ_max = 490 nm) electron-donating bis(naphthylphenylaminophenyl)fumaronitrile (NPAFN). NPAFN exhibits a hole mobility greater than 0.07 cm² V⁻¹ s⁻¹ as determined by its field-effect transistor. It can be attributed to such hole mobility that enables a thin layer (<10 nm) NPAFN in PHJ OPV, ITO/NPAFN/C₆₀/bathocuproine/Al. Because of the low lying HOMO energy level (5.75 eV) of NPAFN and relatively high ionization potential ITO (∼5.58 eV), such OPVs exhibit a very high open circuit voltage of ∼1.0 V, relatively high fill factor of 0.60, and a relatively high shunt resistance of 1100 Ω cm⁻², which all compensate for a relatively low short circuit current of 3.15 mA cm⁻² due to the short absorption wavelength and inferred short exciton diffusion length of NPAFN. Altogether, NPAFN OPVs display a power conversion efficiency (η_PC) of 2.22%, which is better than other long wavelength absorption materials in similar PHJ OPVs, such as pentacene (λ_max 670 nm, HOMO 5.12 eV, η_PC 1.50%) and copper phthalocyanine (λ_max 624, 695 nm, HOMO 5.17 eV, η_PC 1.43%).     

The electrical characteristics of Sn/methyl-red/p-type Si/Al contacts

The junction characteristics of the organic compound methyl-red film (2-[4-(dimethylamino)phenylazo]benzoic acid) on a p-type Si substrate have been studied. The current-voltage characteristics of the device have rectifying behavior with a potential barrier formed at the interface. The barrier height and ideality factor values of 0.73 eV and 3.22 for the structure have been obtained from the forward bias current-voltage (I-V) characteristics. The interface state energy distribution and their relaxation time have ranged from 1.68 × 10¹² cm⁻² eV⁻¹ and 1.68 × 10⁻³ s in (0.73-E_v) eV to 1.80 × 10¹² cm⁻² eV⁻¹ and 5.29 × 10⁻⁵ s in (0.43-E_v) eV, respectively, from the forward bias capacitance-frequency and conductance-frequency characteristics. Furthermore, the relaxation time of the interface states shows an exponential rise with bias from (0.43-E_v) eV towards (0.73-E_v) eV.     

Flexible thin-film transistors using multistep UV nanoimprint lithography

A multistep imprinting process is presented for the fabrication of a bottom-contact, bottom-gate thin-film transistor (TFT) on poly(ethylene naphthalate) (PEN) foil by patterning all layers of the metal–insulator–metal stack by UV nanoimprint lithography (UV NIL). The flexible TFTs were fabricated on a planarization layer, patterned in a novel way by UV NIL, on a foil reversibly glued to a Si carrier. This planarization step enhances the dimensional stability and flatness of the foil and thus results in a thinner and more homogeneous residual layer. The fabricated TFTs have been electrically characterized as demonstrators of the here developed fully UV NIL-based patterning process on PEN foil, and compared to TFTs made on Si with the same process. TFTs with channel lengths from 5 μm down to 250 nm have been fabricated on Si and PEN foil, showing channel length-dependent charge carrier mobilities, μ, in the range of 0.06–0.92 cm² V⁻¹ s⁻¹ on Si and of 0.16–0.56 cm² V⁻¹ s⁻¹ on PEN foil.     

Electrical and photoelectrical properties of P3HT/n-Si hybrid organic–inorganic heterojunction solar cells

A detail analysis of electrical and photoelectrical properties of hybrid organic–inorganic heterojunction solar cells poly(3-hexylthiophene) (P3HT)/n-Si, fabricated by spin-coating of the polymeric thin film onto oxide passivated Si(1 0 0) surface, was carried out within the temperature ranging from 283 to 333 K. The dominating current transport mechanisms were established to be the multistep tunnel-recombination and space charge limited current at forward bias and leakage current through the shunt resistance at reverse bias. A simple approach was developed and successfully applied for the correct analysis of the high frequency C–V characteristics of hybrid heterojunction solar cells. The P3HT/n-Si solar cell under investigation possessed the following photoelectric parameters: J_sc = 16.25 mA/cm², V_oc = 0.456 V, FF = 0.45, η = 3.32% at 100 mW/cm² AM 1.5 illumination. The light dependence of the current transport mechanisms through the P3HT/n-Si hybrid solar cells is presented quantitatively and discussed in detail.     

A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

ZrO₂ thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N′-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H₂O as an oxidizing agent. Tetrakis (ethylmethylamino) zirconium (TEMA-Zr) was also evaluated for a comparative study. Physical properties of ALD-derived ZrO₂ thin films were studied using ellipsometry, grazing incidence XRD (GI-XRD), high resolution TEM (HRTEM), and atomic force microscopy (AFM). The ZrO₂ deposited using Zr-AMD showed a better thermal stability at high substrate temperature (>300 °C) compared to that using TEMA-Zr. GI-XRD analysis reveals that after 700 °C anneal both ZrO₂ films enter tetragonal phase. The electrical properties of N₂-annealed ZrO₂ film using Zr-AMD exhibit an EOT of 1.2 nm with leakage current density as low as 2 × 10⁻³ A/cm² (@V_fb−1 V). The new Zr amidinate is a promising ALD precursor for high-k dielectric applications.     

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current–voltage (I–V) characteristics are reported of metal–insulator–metal (MIM) and metal–insulator–semiconductor (MIS) capacitors employing cross-linked poly(amide–imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10 Hz to 100 kHz, with tan δ values as low as 7 × 10⁻³ over most of the range. Except at the lowest voltages, the I–V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell–Wagner frequency response from which the transverse bulk hole mobility was estimated to be ∼2 × 10⁻⁵ cm² V⁻¹s⁻¹ or ∼5 × 10⁻⁸ cm² V⁻¹s⁻¹ depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be ∼5 × 10¹⁰ cm⁻² eV⁻¹ or ∼9 × 10¹⁰ cm⁻² eV⁻¹ again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices.     

Characterization of polycrystalline 3C-SiC thin film diodes for extreme environment applications

This paper describes the fabrication and characteristics of polycrystalline (poly) 3C-SiC thin film diodes for extreme environment applications, in which the poly 3C-SiC thin film was deposited onto oxidized Si wafers by APCVD using HMDS as a precursor. In this work, the optimized growth temperature and HMDS flow rate were 1100 °C and 8 sccm, respectively. A Schottky diode with a Au, Al/poly 3C-SiC/SiO₂/Si(n-type) structure was fabricated and its threshold voltage (V_d), breakdown voltage, thickness of depletion layer, and doping concentration (N_D) values were measured as 0.84 V, over 140 V, 61 nm, and 2.7 × 10¹⁹ cm³, respectively. To produce good ohmic contact, Al/3C-SiC were annealed at 300, 400, and 500 °C for 30 min under a vacuum of 5.0 × 10⁻⁶ Torr. The obtained p-n junction diode fabricated by poly 3C-SiC had similar characteristics to a single 3C-SiC p-n junction diode.