DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.     

Majority Logic Mapping for Soft Error Dependability

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. A new type of voter circuit, that uses some knowledge from the analog design arena is proposed, together with a new mapping approach to implement circuits given their input/output table. This new mapping approach is shown to compare favorably against a classic mapping. The implementation and validation of an adder circuit, using conventional triple modular redundancy (TMR), the classic mapping, and the proposed solution are analyzed, in order to confirm that the shown technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR. Finally, implementations of a subset of the ISCAS 85 benchmark circuits using TMR with the analog voter and the proposed approach are compared and the results analyzed.     

Research on the packing algorithm for anti-SEU of FPGA based on triple modular redundancy and the numbers of fan-outs of the net

Static Random Access Memory （SRAM） based Field Programmable Gate Array （FPGA） is widely applied in the field of aerospace,whose anti-SEU （Single Event Upset） capability becomes more and more important.To improve anti-FPGA SEU capability,the registers of the circuit netlist are tripled and divided into three categories in this study.By the packing algorithm,the registers of triple modular redundancy are loaded into different configurable logic block.At the same time,the packing algorithm considers the effect of large fan-out nets.The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy （TMR）.Comparing with Timing Versatile PACKing （TVPACK）,the algorithm in this study is able to obtain a 11％ reduction of the number of the nets in critical path,and a 12％ reduction of the time delay in critical path on average when TMR is not considered.Especially,some critical path delay of circuit can be improved about 33％.     

Partial evaluation based triple modular redundancy for single event upset mitigation

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.     

A Practical Tantalum Thin-Film Single-Sideband Demodulator Using RC Time-Varying and Active Networks

The thin-film circuit described in this paper is equivalent to a demodulator circuit containing an extremely selective filter ("sideband" filter). Such a filter would, in conventional form, require very high Q inductors or, as the Q requirement increases, the use of crystal or mechanical filters. At the frequency of operation of this circuit (1 MHz), demodulation with conventional filters would have to be accomplished in two or more stages so that the selectivity requirement can be decreased for each filter. Thin-film techniques restrict us to circuits using only resistors (R), capacitors (C), and added semiconductor devices (thin-film inductors are not considered here since their inductance values are too small). The current trend is to realize frequency selective networks (conventionally in LC form) as active RC networks. However, although the circuit described here incorporates such a network, the main selectivity requirement cannot be met by present-day active network techniques. The solution is found in the use of time-varying RC networks, i.e., by combining passive RC thin-film phase-shift networks with miniature transistors, used as electronic switches, in the form of so-called quadrature modulation circuits. The phase-shift networks, which in principle can be passive thin-film RC circuits, are in practice more easily realized as combinations of much simpler RC circuits with buffer amplifiers.     

FPGA三模冗余工具的关键技术与发展

SRAM型现场可编程门阵列(FPGA)在空间辐射环境中容易受到单粒子效应的影响,从而发生软错误,三模冗余技术(TMR)是目前使用最广泛的缓解FPGA软错误的电路加固技术。该文首先介绍了三模冗余技术研究现状,然后总结了三模冗余工具常用的细粒度TMR技术、系统分级技术、配置刷新技术、状态同步技术4项关键技术及其实现原理。随着FPGA的高层次综合技术愈发成熟,基于高层次综合的三模冗余工具逐渐成为新的研究分支,该文分类介绍了当前主流的基于寄存器传输级的三模冗余工具,基于重要软核资源的三模冗余工具,以及新兴的基于高层次综合的三模冗余工具,最后对FPGA三模冗余工具的未来发展趋势进行了总结与展望。     

Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study

The problem of radiation is a key issue in Space applications, since it produces several negative effects on digital circuits. Considering the high reliability expected in these systems, many techniques have been proposed to mitigate these effects. However, traditional protection techniques against soft errors, like Triple Modular Redundancy (TMR) or EDAC codes (for example Hamming), normally result in a significant area and power overhead. In this paper we propose a specific technique to protect digital finite impulse response (FIR) filters applying the “system knowledge”. This means to study and use the singularities in their structure in order to provide effective protection with minimal area and power. The results obtained in the experimental process have been compared with the protection offered by TMR and Hamming codes, in order to prove the quality of the proposed solution.     

Design of Symmetrical Class E Power Amplifiers for Very Low Harmonic-Content Applications

Class E power amplifier circuits are very suitable for high efficiency power amplification applications in the radio-frequency and microwave ranges. However, due to the inherent asymmetrical driving arrangement, they suffer significant harmonic contents in the output voltage and current, and usually require substantial design efforts in achieving the desired load matching networks for applications requiring very low harmonic contents. In this paper, the design of a Class E power amplifier with resonant tank being symmetrically driven by two Class E circuits is studied. The symmetrical Class E circuit, under nominal operating conditions, has extremely low harmonic distortions, and the design of the impedance matching network for harmonic filtering becomes less critical. Practical steady-state design equations for Class E operation are derived and graphically presented. Experimental circuits are constructed for distortion evaluation. It has been found that this circuit offers total harmonic distortions which are about an order of magnitude lower than those of the conventional Class E power amplifier.     

Seamless Pipelining of DSP Circuits

Pipelining is a popularly used technique to achieve higher frequency of operation of digital signal processing (DSP) applications, by reducing the critical path of circuits. But conventionally critical path is estimated by the discrete component timing model in terms of the times required for the computation of additions and multiplications, where arithmetic circuits are considered as discrete components. Pipeline registers are inserted in between arithmetic circuits to reduce the estimated critical path. In this paper, we show that very often the architecture-level pipelining, based on the discrete component timing model, does not result in significant reduction in critical path, but on the other hand increases the latency and register complexity. In order to derive greater advantage of pipelining, propagation delays of different combinational sections could be evaluated precisely at gate level or at least at the level of one-bit adders, and based on that, the critical path could be reduced by placing the pipeline registers seamlessly across the combinational datapath without restricting them to be placed only in between arithmetic circuits. In this paper, we present adequately precise evaluation of propagation delays across combinational path as a network of arithmetic circuits based on seamless view of signal propagation. Using the precise information of propagation delay of combinational sections, we identify the best possible locations of pipeline registers in order to reduce the critical path up to the desired limit. The proposed seamless pipelining approach is found to achieve the desired acceleration of DSP applications without significant pipeline overhead in terms of latency and register complexity.     

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST

In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit.     

Switched-capacitor discrete Fourier analyser with window function circuit

An analogue window function circuit is realized by using switched-capacitor techniques. In order to verify the effect of this window, a novel switched-capacitor analogue discrete Fourier analyser is proposed. The window function circuit is included in this analyser as the ratios of capacitances. This switched-capacitor discrete Fourier analyser is very simple in construction, namely, only two elemental circuits based on the integral feedback capacitance circuit are connected in series. Agreement between the experimental and the theoretical values is confirmed.     

Circuit related issues due to radiation in hostile environments

Various types of radiation in hostile environments cause transient and permanent changes in the devices used in complex integrated circuits. The failure of a particular IC is a function not only of the basic material and device parameter changes but also of the circuit environment in which the device is located. Circuit techniques have been developed which minimize the detrimental effects of radiation on certain types of circuits. In other cases, circuit techniques are not very effective in minimizing radiation effects. This work discusses selected issues related to the interactions between device radiation effects and circuit performance or circuit failure in a hostile radiation environment. This is not meant to be a comprehensive study of circuit effects but rather several examples are selected to illustrate the issues involved in designing circuits to operate in hostile radiation environments.     

基于模代数的三值维持阻塞触发器及其应用

本文给出了基于模代数理论的三值维持阻塞触发器,并将其应用到时序逻辑电路设计中。由于多值模代数中的两个基本运算和运算结果均为多值信号,所以它的应用避免了以往在采用基于Ｐｏｓｔ代数的三值触发器时,由于输入、输出信号不匹配而必须增加附加编码电路的问题。设计实例表明,该触发器具有更强的逻辑功能,它使得移位寄存器类的时序电路设计得以显著简化。     

A Low-Power Multiphase Circuit Technique

The principle of multiphase MOS digital circuits is briefly discussed and the features of some presently used multi-phase schemes are given. The basic theory and implementation of a six-phase scheme, which make use of a basic principle not normally considered in low-power digital circuitry, are then described, and the first-order equations for power dissipation are derived. The theoretical power dissipation of a six-phase shift register is compared to the power dissipation of equivalent shift registers using other low-power circuit techiques, including the complementary MOS transistor technique, and it is shown that the six-phase technique has the lowest power dissipation from very low frequencies up to a limiting high frequency. Finally, the power dissipation of an actual six-phase circuit is compared to the dissipation predicted from the derived equations.     

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.     

面向硬件仿真的SystemVerilog断言检查电路生成研究

提出了一种针对SystemVerilog断言的断言检查电路综合方法。综合而成的断言检查电路可以被用于硬件仿真中。方法基于移位寄存器链保存电路信号的历史数据,并利用断言电路间寄存器共用减少硬件资源使用。实验结果表明,与已有的断言综合方法比较,本方法具有有效性。