Ge volatilization products in high-k gate dielectrics

GeO molecules are often emitted by Ge substrates under high-temperature annealing and, in the case of gate stacks, they diffuse through high-k oxides. Here we use first-principles quantum-mechanical calculations to probe the stability of these impurities in La₂O₃ and HfO₂ and their effect on the electronic properties of the host systems. We find that the GeO species introduce several different levels inside the energy band gaps of La₂O₃ and HfO₂. As a result, the impurities may act as charge carrier traps. Hydrogenation of the GeO defects modifies the position and numbers of gap states, but does not eliminate the carrier trap levels completely. The results suggest a possible role of Ge volatilization in enhancing leakage currents and degradation in high-k gate stacks of Ge-based devices.     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Process integration of Pr-based high-k gate dielectrics

We present the process integration of the Pr-based high-k oxides Pr₂O₃, PrTi_xO_y and Pr_xSi_yO_z for CMOS devices. MOS structures were grown in form of p⁺ poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF₄/O₂ plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H₂SO₄ solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated Pr_xSi_yO_z are presented.     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

Effects of deuterium anneal on MOSFETs with HfO/sub 2/ gate dielectrics

The effects of high-temperature (600/spl deg/C) anneal in a dilute deuterium (N/sub 2/ : D/sub 2/= 96 : 4) atmosphere was first investigated and evaluated in comparison to high-temperature forming gas (N/sub 2/ : H/sub 2/= 96 : 4) anneal (600/spl deg/C) and nonanneal samples. The high-temperature deuterium anneal was as effective as the forming gas anneal in improving MOSCAP and MOSFET characteristics such as the C-V curve, drain current, subthreshold swing, and carrier mobility. These can be attributed to the improved interface quality by D/sub 2/ atoms. However, unlike the forming gas anneal, the deuterium anneal provided the hafnium oxide (HfO/sub 2/) gate dielectric MOSFET with better reliability characteristics such as threshold voltage (V/sub T/) stability under high voltage stress.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

A nanoanalytical investigation of high-k dielectric gate stacks for GaAs based MOSFET devices

In this paper a quantitative determination of the elemental distributions across a ∼10 nm Ga₂O₃/GdGaO layer with a Pt metal gate cap on top of an InGaAs/AlGaAs/GaAs substrate is presented. Some effects of annealing on the elemental distribution across the Ga₂O₃/GdGaO oxide layer are described. The paper also discusses the analysis of the interface GaAs/Ga₂O₃/GGO at a sub-nm level by high-resolution HAADF STEM imaging.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.     

Effect of interfacial fluorination on the electrical properties of the inter-poly high-k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al₂O₃ and HfO₂ IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO₂ possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al₂O₃ dielectric is more effective to promote the IPD characteristics than fluorination of the HfO₂ dielectric. For future stack-gate flash memory application, the fluorinated Al₂O₃ IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO₂ IPD due to superior insulating properties.     

Thickness optimization of the TiN metal gate with polysilicon-capping layer on Hf-based high-k dielectric

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10 nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

Performance and optimisation of dual material gate short channel BULK MOSFETs for analogue/mixed signal applications

The challenge of analogue operation of CMOS devices and its parameters is a very important study for future technologies. In this article, the performance of dual material gate bulk MOSFETs for analogue/mixed signal applications is explored. Moreover, the optimisation of the device is done based on the variation of length and work-function difference of the two gate metals. The effect of drain induced barrier lowering in this structure is studied in detail. Moreover the different analogue parameters such as transconductance (g _m), output resistance (R _o) tuning for high performance of the device are also investigated by extensive simulations.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Hot carrier degradation mechanisms in sub-micron p channel MOSFETs: Impact on low frequency (1/f) noise behaviour

In this work we present new results which illustrate the impact of hot carrier (HC) degradation on the low frequency (1/f) noise behaviour of submicron p channel MOSFETs. Submicron p channel MOSFETs were subjected to HC stress at a range of gate bias conditions, and the response of the low frequency noise was recorded. The results obtained are in marked contrast to the reported influence of HC stress on nMOSFETs 1/f noise, and indicate that the measurement of 1/f noise is a useful tool for investigating HC induced aging effects in submicron p channel devices. The significance of these results to the use of pMOSFETs in analog applications is briefly discussed.     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

Dependence of hot-carrier immunity on channel length and channelwidth in MOSFETs with N2O-grown gate oxides

The authors report on the channel length (0.5-5 μm) and width (0.6-10 μm) dependence of hot-carrier immunity in n-MOSFETs with N ₂O-grown gate oxides (~85 Å). While channel hot-carrier-induced degradation has a strong dependence on channel geometry in control devices, the degradation and its channel geometric dependences are greatly suppressed in devices with N₂O-gate oxides. Under Fowler-Nordheim injection stress, the control device shows an enhanced degradation with decreasing channel length and increasing channel width, whereas N₂O device exhibits a less dependence on channel geometry     

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel.The present model is valid in linear and saturation regions of device operation.The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect.Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated.The model results are validated by numerical simulation results obtained by using the commercially available ATLAS^TM,a two dimensional device simulator from SILVACO.     

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO/sub 2/ gate dielectrics

Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.