A plug-and-play wideband RF circuit ESD protection methodology: T-diodes

A novel “plug-and-play” ESD protection methodology for wideband RF applications is demonstrated. This methodology, referred to as T-diodes, utilizes an integrated transformer together with classical ESD protection diodes. The T-diodes act as an artificial transmission line that, when placed as a “plug-and-play” ESD protection component in front of an unprotected wideband LNA, preserves the input matching of that LNA. As a demonstrator, a wideband RF LNA in 0.18 μm CMOS is protected above 4.5 kV HBM ESD robustness without degrading its bandwidth.     

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme was modified from the conventional double-diode ESD protection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.     

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.     

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

Cancellation technique to provide ESD protection for multi-GHz RF inputs

A technique to provide ESD protection for multi-GHz R-F inputs is presented. It provides protection against both human body model (HBM) and charged device model (CDM) type events with minimal effect on RE performance. A 5.25 GHz LNA protected by this means has a measured HBM ESD protection level of 3.6 kV.     

Electrical overstress due to ESD induced displacement currents

In this paper a new failure mode is introduced, which is related to the large dV/dt of ESD pulses. It was observed after +4 kV HBM stress for a 90V-BCD technology device and resulted in a gate oxide defect of a low voltage PMOS transistor, which was hidden deeper in the IC's circuitry. The underlying failure mechanisms are discussed based on experimental and simulational findings and measures for early identification and protection of potentially sensible devices are proposed.     

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection     

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [forGPS receiver]

In recent years, much research has been carried out on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies, for radio-frequency (RF) applications. An example of such an application is the Global Positioning System (GPS). One of the important bottlenecks to make the transition to pure CMOS is the immunity of the circuits against electrostatic discharge (ESD). This paper shows that it is possible to design a low-noise amplifier (LNA) with very good RF performance and sufficient ESD immunity by carefully co-designing both the LNA and ESD protection. This is demonstrated with a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human body model (HBM) with a power consumption of 9 mW. The circuit was designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is implemented in a standard 0.25-μm 4M1P CMOS process     

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ${sim}2$ nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient $S_{11}$ is below ${-}13.0$ dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ${sim}40$ fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ${sim}100$ V/fF) among the published results for RF LNA applications.      

New considerations for MOSFET power clamps

Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6 kV and CDM pulses of 1.2 kV.     

Ultra low voltage, ultra low power low noise amplifier for 2 GHz applications

In this paper, a 0.29 V, 2 GHz CMOS low noise amplifier (LNA) intended for ultra low voltage and ultra low power applications is developed. The circuit is simulated in standard 0.18 μm CMOS MOSIS. A two-stage architecture is then used to simultaneously optimize the gain and noise performance. Using forward-body-biased, the proposed LNA can operate at 0.29 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The LNA provides a good gain of 26.25 dB, a noise figure of 2.202 dB, reverse isolation (S₁₂) of −59.04 dB, input return loss (S₁₁) of −122.66 dB and output return loss (S₂₂) of -11.61 dB, while consuming only 0.96mW dc power with an ultra low supply voltage of 0.29 V. To the best of authors’ knowledge this is the lowest voltage supply and the lowest power consumption CMOS LNA design reported for 2 GHz to date.     

一种提高ESD性能的高压SBD器件结构研究

提出了一种新型SBD器件结构,并应用于高压SBD产品的研制。该结构通过在肖特基势垒区的硅表面增加一层表面缓冲掺杂层(Improved Surface Buffer Dope),将高压SBD的击穿点从常规结构的PN结保护环区域转移到平坦的肖特基势垒区,从根本上提高了器件的反向静电放电(ESD)和浪涌冲击能力。经流片验证,采用该结构的10A150VSBD产品和10A200VSBD产品均通过了反向静电放电(HBM模式)8kV的考核,达到目前业界领先水平。该结构工艺实现简单,可以应用于100V以上SBD的批量生产。     

A dual front-end for the new GPS/GALILEO generation in a 0.35 μm SiGe process

A highly integrated, low-power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 μm SiGe process. First an analysis of the current and future GPS and GALILEO signals is presented in order to show the interoperability between both systems and to set the requirements for the entire front-end. The receiver has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4.092 MHz after digitalization. The ESD protected RF front-end exhibits a voltage gain of 103 dB and an SSB noise figure of 3.7 dB, which makes it suitable for high-sensitivity applications. The achieved power consumption is only 66 mW from a 3 V voltage supply and 38 mW if the internal dual-gain LNA is switched off with no compromise with performance and with a minimal amount of external components.     

Wide range control of the sustaining voltage of electrostatic discharge protection elements realized in a smart power technology

Highly efficient electrostatic discharge (ESD) protection structures with a sustaining voltage >40 V are realized in a smart power technology. They guarantee an excellent ESD protection at high voltage pins without the danger of transient latch-up. Compared to the vertical npn transistor a shift of the sustaining voltage of 21 V has been achieved purely by a layout modification of the buried layer. The high ESD performance has been proven on product level by an ESD hardness of >8 kV (HBM).     

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology

BiCMOS technologies have been used to implement the radio-frequency (RF) integrated circuits (ICs) due to the advantages of low noise, low power consumption, high drive, and high speed. The electrostatic discharge (ESD) is one of the important reliability issues of IC. When the ESD events happen, the ESD protection devices must be turned on immediately to protect the ICs, including the RF ICs in BiCMOS technologies. In this work, the vertical NPN (VNPN) devices in 0.18 μm silicon-germanium (SiGe) BiCMOS technology with base-emitter shorted and resistor trigger approaches are investigated. In component-level, using transmission-line-pulsing (TLP) and ESD simulator test the IV characteristics and human-body-model (HBM) robustness of the VNPN devices, respectively. In system-level, using ESD gun tests the system-level ESD robustness. The ESD protection of VNPN devices are further applied to a 2.4 GHz low-noise amplifier (LNA). After attaching the VNPN devices to LNA, the RF characteristics are not degraded while the ESD robustness can be much improved.     

A double RESURF LDMOS with drain profile engineering for improvedESD robustness

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I_t2) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size     

On a dual-polarity on-chip electrostatic discharge protectionstructure

A novel dual-polarity on-chip electrostatic discharge (ESD) protection structure is designed. The new ESD structure protects IC chips against ESD stressing in the two opposite directions. The ESD structure features symmetric deep-snapback current-voltage (I-V) characteristics, low-impedance active overcurrent discharging path, low holding voltage for overvoltage clamping, fast ESD response of ~0.18 ns, low leakage (~pA), adjustable triggering voltage, and good scalability. It passes 14 KV HBM ESD zapping tests and achieves high ESD-performance-to-Si ratio of ~80 V/μm width. The new ESD structure reduces Si areas consumed by ESD protection units and ESD-induced parasitic effects significantly     

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

A new design on the electrostatic discharge (ESD) protection scheme for CMOS IC operating in power-down-mode condition is proposed. By adding a VDD_ESD bus line and diodes, the new proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. Experimental results have verified that the human-body-model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-μm silicided CMOS process. Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition.