高温可靠性试验对SiC MOSFET特性参数的影响

SiC MOSFET可以提升电力电子器件的功率密度,在特高压直流输电、电动汽车等领域有较好的应用前景,但其特性参数的分散性会影响器件的长期稳定运行.对SiC MOSFET进行了168 h的高温栅偏(HTGB)和高温反偏(HTRB)试验.结果 表明,试验前后器件的阈值电压和跨导变化较大,而导通电阻和极间电容变化较小.通过拟合分析得到试验前后器件导通电阻、阈值电压和跨导的变化率与各参数数值之间的拟合曲线.最后基于测试结果,提出了一种针对1 200 V/20 A SiC MOSFET的筛选方法,以降低器件在高温可靠性试验前后的参数变化率,从而提升器件在长期高温环境中的可靠性.     

CMOS工艺制备的高压PMOSFET温度特性研究

采用Cascade探针台与Agilent 4155B参数测试仪测试采用1.5μmP阱单层多晶单层金属CMOS工艺制作的宽长比为50∶4的高压PMOSFET在不同温度下(27°C～200°C)的器件特性,包括漏电流I_(DS)、阈值电压V_T、栅跨导gm的温度特性,并与常压PMOSFET温度特性比较,推导阈值电压值与温度的简单关系。     

对称薄膜双栅nMOSFET模型的研究

利用对称薄膜双栅MOSFET在阈值电压附近硅膜中的常电位近似,以硅膜达到体反型时的泊松方程为基础,得到一个有效的双栅nMOS器件模型.考虑到薄膜双栅SOI器件的体反型特性,阈值电压处的表面势不再受限于传统的强反型界限(指2倍费米势),并运用跨导最大变化(TC)法对此模型进行分析,得到阈值电压和阈值电压处表面势的详细表达式;另外,还演示了薄膜双栅MOSFET的近乎完美的亚阈值斜率特性,其数值模拟结果与文献实验结果吻合较好.     

功率MOSFET器件栅电荷测试与分析

栅电荷是表征功率MOSFET器件动态特性的重要参数之一,其测试结果与时间和频率有关,受分布参数、测试夹具和电路结构等因素影响较大。其参数直接影响器件整体性能,设计不好将导致器件没使用时已击穿甚至损坏,在军用功率MOSFET器件研制生产和使用验收中列为必测参数。随着对MOSFET器件可靠性要求的不断提高,栅电荷的测试重要性凸显。针对目前国内外栅电荷测试现状及存在的问题做了详尽阐述,为国内的栅电荷测试提供一定的参考和指导。     

碳化硅MOSFET电学参数的电容-电阻法评估

阈值电压、栅内阻、栅电容是碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)的重要电学参数,但受限于器件寄生电阻、栅介质界面态等因素,其提取过程较为复杂且容易衍生不准确性。文章通过器件建模和实验测试,揭示了MOSFET的栅电容非线性特征,构建了电容-电阻串联电路测试方法,研究了SiC MOSFET的栅内阻和阈值电压特性。分别获得栅极阻抗和栅源电压、栅极电容和栅源电压的变化规律,得到栅压为-10V时的栅内阻与目标值误差小于0.5Ω,以及串联电容相对栅源电压变化最大时的电压近似为器件阈值电压。相关结果与固定电流法作比较,并分别在SiC平面栅和沟槽栅MOSFET中得到验证。因此,该种电容-电阻法为SiC MOSFET器件所面临的阈值电压漂移、栅极开关振荡现象提供较为便捷的评估和预测手段。     

射频功率Trench MOSFET研制

在国内首次研制出了一种采用条状元胞结构、特殊的栅槽刻蚀条件、特殊的栅介质生长前处理工艺及多晶硅栅的射频功率Trench MOSFET器件。该器件漏源击穿电压大于62V、漏极电流大于3.0A、跨导大于0.8S、阈值电压2~3V、导通电阻比同样条件的VDMOS降低了19%~43%,在175MHz、VDS=12V下输出功率PO为7W、漏极效率ηD为44%、功率增益GP为10dB。     

65nm n沟MOSFET的重离子辐照径迹效应研究

重离子在SiO2中能产生永久径迹,因此它可能对MOS器件电学特性产生影响。文章用Geant4软件对Au和Sn两种离子进行蒙特卡洛模拟,重点分析高能粒子在SiO2中的能量沉积及径迹。基于模拟分析,对专门设计的65 nm n沟MOSFET器件进行Sn离子辐照实验,发现辐照后Ids和Ig明显增大,分析器件辐照前后阈值电压、跨导、沟道电流以及栅漏电流等特性参数变化的原因。     

F-N应力下SOI n-MOSFETs性能退化与栅控二极管产生-复合（G-R）电流的对应关系

本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合（G-R）电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合（G-R）电流增大,以及MOSFET饱和漏端电流,亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试,实验观察到饱和漏端电流的线性退化和阈值电压的线性增加,亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。     

碳化硅MOSFET的高温栅偏特性

针对碳化硅(SiC)MOSFET存在的栅氧可靠性问题,对其展开高温栅偏(HTGB)试验研究。以阈值电压(V_TH)和体二极管通态压降(V_SD)作为特征参数,设计搭建应力及测试试验平台,研究SiC MOSFET在高温栅偏应力下的特征参数退化特性,并对短期恢复下特征参数的不稳定现象以及长期恢复对特征参数的影响进行了分析。试验结果表明,SiC MOSFET的V_TH和V_SD均受负向和正向高温栅偏的影响,并能够产生相反方向的参数漂移。撤去应力后存在恢复现象,使电参数受可恢复部分偏移量的影响具有不稳定性,且经过长期室温储存后仍存在进一步的恢复。     

基于ABM器件的SiC MOSFET建模研究

针对不同温度下SiC MOSFET模型精度不足的问题,提出一种基于模拟行为模型(ABM)器件建立SiC MOSFET模型的方法.分别对整体模型的沟道电流、导通电阻和栅漏电容部分进行改进,引入了阈值电压和跨导系数的温度调节函数,考虑了温度和栅源电压对导通电阻的影响,提出了无开关栅漏电容,建立了满足连续温度仿真的SiC M...     

Characteristics of enhancement/depletion (E/D) gate MOSFET fabricated using ion implantation

The E/D gate MOSFET, which has an enhancement and depletion mode region under the same gate, is fabricated by using ion implantation as a tool for shifting threshold voltage. Threshold voltage, transconductance and drain breakdown voltage are studied as functions of implantation dose up to 12 × 10¹² cm^?2.It is found that, at an appropriate dose, the transconductance of this device is determined solely by the channel length of the enhancement mode region, and is larger than that of a short channel MOSFET with a standard structure but with the same drain breakdown voltage. Moreover, the dependence of threshold voltage on substrate bias measured in this device is found less sensitive to the transconductance than that in the standard short channel MOSFET.     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET

This paper reports the effects of bias temperature stress (positive and negative bias temperature instabilites, PBTI–NBTI) on threshold voltage, input capacitance and Miller capacitance of N-Channel Power MOSFET. The device is stressed with gate voltage under precision temperature forcing system. The bias temperature cycling also induces instabilities N-Channel Power MOSFET. The gate charge characteristics have been investigated before and after stress. The capacitances (the drain–gate and drain–source capacitances) are shifted due to the degradation of device physical properties under different stress time and stress temperature conditions. Bi-dimensional simulations have been performed for the 2D Power MOSFET structure and accurately analyzed. Gate charge characteristics of the device have been correlated to physical properties to analyze mechanisms responsible of parameter degradations. It is shown that the main degradation issues in the Si Power MOSFET are the charge trapping and the trap creation at the interface of the gate dielectric performed by energetic free carriers, which have sufficient energy to cross the Si–SiO₂ barrier.     

Comparison of -MOSFET lifetime estimates based on GIDL enhancement and transconductance degradation as criteria

A comparison of MOSFET lifetimes based on gate-induced drain leakage (GIDL) enhancement and transconductance degradation as criteria is presented. Analysis of damage mechanisms indicates that degradations related to interface state generation limit the MOSFET lifetime at reduced voltage operations. In conventional gate oxide MOSFETs, GIDL enhancement due to band-to-defect tunneling and transconductance degradation limit the lifetime at reduced voltage. For MOSFETs with reoxidized nitrided gate oxides, our results show that GIDL enhancement due to band-to-defect tunneling is a better reliability monitor than transconductance degradation at low operating voltages.     

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1-μm-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO₂ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed     

A review of recent MOSFET threshold voltage extraction methods

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET.     

A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si

We have fabricated an enhancement-mode n-channel Schottky-barrier-MOSFET (SB-MOSFET) for the first time on a high mobility p-type GaN film grown on silicon substrate. The metal contacts were formed by depositing Al for source/drain contact and Au for gate contact, respectively. Fabricated SB-MOSFET exhibited a threshold voltage of 1.65 V, and a maximum transconductance(g/sub m/) of 1.6 mS/mm at V/sub DS/=5V, which belongs to one of the highest value in GaN MOSFET. The maximum drain current was higher than 3 mA/mm and the off-state drain current was as low as 3 nA/mm.     

SiGe-channel n-MOSFET by germanium implantation

The first n-SiGe-channel MOSFETs fabricated using high-dose germanium implantation and solid-phase epitaxy are reported. The polysilicon-gate MOSFETs were fabricated in the same chip in which conventional polysilicon-gate n-MOSFETs were made and their electrical characteristics are compared. The SiGe-channel MOSFETs show some significantly better electrical characteristics as compared to the silicon-channel MOSFETs. For example, the SiGe MOSFETs show higher drain conductance in the triode region and higher transconductance overall. The threshold voltage of the SiGe MOSFET appears to be smaller and the carrier mobility in the channel appears to be higher     

VDMOS的虚拟栅结构

文中设计了一个虚拟栅结构的VDMOS,该结构可以减小漏栅反馈电容Cras,使其接近于零.因此,对于相同的模块电压率,虚拟栅结构可以使MOS器件有一个更短的沟道,同时也因为有一个更大的栅漏交叠区域而使导通电阻减小.这样,器件跨导也可以提高.经过ISE仿真模拟,虚拟栅结构比原始分栅结构的击穿电压提高了近42%,而电流输出特性也更好更稳定.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.