二维高速激光切割机控制系统的研究

介绍一种新型二维激光切割机控制系统。该控制系统采用上位PC和下位DSP控制板结合的方式工作，下位机采用DSP和FPGA组合方式工作。利用高速DSP的强大运算能力和FPGA的硬件实时特性，采用改进的脉冲增量插补算法计算，有效提高了激光切割机的加工速度，最高切割速度达到2 m/s。     

浮点多字节重叠扫描乘法运算方法

在扫描运算的基础上，介绍了一种重叠扫描算法来提高浮点多字节乘法运算的速度。     

多核浮点非线性运算协处理器的设计与实现

在载人航天飞船的终端仪器仪表设计中,处理算法中的浮点非线性运算常采用库函数实现,但软件实现非线性函数执行速度慢,限制了浮点算法的应用。为此,针对航天领域处理器不支持非线性函数运算的情况以及浮点算法执行速度慢的问题,提出一种多核并行执行浮点非线性运算处理方法,利用现场可编程门阵列内部并行架构带来的低延迟特性来提高非线性浮点运算的速度。仿真实验结果表明,该方法可计算有限定义域范围内的浮点非线性函数,有效提高浮点运算的执行速度。     

基于GPU实现的AES加密

高级加密标准(Advanced Encryption Standard,AES),在密码学中又称Rijndael加密法,是美国联邦政府采用的一种区块加密标准。该算法已经被多方分析论证并广为全世界所使用。传统的AES加密运算是在CPU上实现的,现在为了提高加密速度以处理大规模的加密运算,文中提出了一种在图像处理器(Graphics Processing Unit)上实现AES加密算法的方法。该方法的实现有两种,一种是基于传统OpenGL的AES实现,另一种是基于最新技术CUDA的AES实现。文中阐述的是前者。经过测试,该方法比传统CPU的实现提高了15到40倍左右的速度。     

基于数学形态的灰度线形态识别研究与开发

灰度线形态特征识别是许多工程模式识别系统的重要部分，该文提出了一种采用CB形态滤波的算法来提取线形态，并结合结构元素分解的方法加快图像处理的运算速度，使识别算法在速度和效果方面都得到了较大提高。     

模重复平方算法的rho改进算法

利用循环二进制方法给出了适合大指数模乘运算的模重复平方算法的rho改进算法,以提高模幂乘法的计算速度。新算法的实质是一种指数约减算法,可以有效减少模重复平方算法中的模乘运算。通过实例计算表明,新算法可以极大地提高运算速度。     

利用重叠扫描方法改进单片机乘法运算

目前微型机运算的速度成级数上升,加之数据运算的专门高速处理系统如ＤＳＰ的开发利用,使人们忽视了计算机基本运算的算法研究。然而在许多场合,如需要高精度运算的简易系统中,高速高精度的算法往往直到决定性作用;同时,好的算法在快速运算器件上的应用可以使其速度更快,而且对系统的设计提供了很大的帮助。因而本文在扫描运算的基础上,介绍了一种重叠扫描算法来提高单片机浮点多宇节算法运算的速度。     

GPS信号串行捕获算法研究

传统串行搜索算法在时域内对所有可能的频点和相位进行串行搜索,搜索的过程只需要加法和乘法运算,无论是在硬件还是软件中都容易实现,在GPS接收机设计中得到大量应用.但由于串行搜索算法在实际接收机中实现时,捕获过程需要大量的相乘、累加运算,需要较长的捕获时间.文中从降低相乘和累加运算个数入手,提出一种改进算法,使得捕获速度得到明显提高.利用MATLAB分别对传统的和改进的算法进行了算法仿真;根据信号捕获理论结合仿真实验结果,对两种算法进行了比较和分析,认为改进算法可以有效的应用于GPS信号捕获,而且提高了捕获的速度.该算法时于其它系统的伪随机码捕获也是适用的.     

线性规划在椭圆曲线密码系统中的应用

提高椭圆曲线上点加运算的速度在整个基于FPGA设计的椭圆曲线密码应用系统实现中极为关键。在对已有的几种投影坐标系下的点加运算进行分析比较的基础上,提出了一种适合于FPGA设计实现的椭圆曲线上的点加运算方案。同时结合椭圆曲线密码系统具体约束给出了整数线性规划算法,并将该算法应用干曲线点加算法的并行优化处理。试验结果表明,优化后的投影坐标下的点加运算较原来的算法在速度上提高了22％。     

中值滤波均值快速算法在高光谱图像处理系统中的应用

文章提出了一种中值滤波均值快速算法，介绍了该算法的设计思路、算法流程、基本运算步骤、实验设计与效果及与经典算法的比较情况。该算法利用数据窗口中的位置关系并考虑了相邻的两个中值滤波窗口内信号数据的相关性，在运算过程中，保留前面窗口内数据的排序信息，作为下一个窗口内数据排序的参考依据。这样可将传统算法中相邻的两次中值滤波运算合并为一次进行，减少了中值滤波过程中比较运算的次数，该算法可将传统算法的复杂度O(n^2)简化成O(n)，同时将均值滤波与中值滤波有机结合起来，将两个独立的算法有机地融合成一种算法，从而有效提高运算速度，也减少噪声对图像的影响。     

用于小目标检测的TDNLMS自适应预测器结构优化

讨论用于小目标检测的TDNLMS(Two-Dimensional Normalized Least Mean Square)自适应预测器VLSI实现中的结构优化问题．通过分析小目标图像的特点，使预测器直接处理隔行扫描图像，从而取消了帧存环节，大大减少了片内存储器数量．另外，在基本保持检测性能的基础上，通过对算法进行优化，提高了预测器的工作速度．达到实时图像处理．实验证明本方案不仅提高了预测器的数据通过率．而且简化了硬件电路，降低了设计难度．是一种为合理的方案．     

基于并行处理的混合自适应控制器

本文研究采用并行处理技术产现对象具有未建模动态时的间接式混合自适应控制算法并重新设计了周期协方差重置序列最小二乘和补偿器增益计算方法，给出便于超大规模集成电路脉动阵列实现的结构，加快了高速高性能自适应控制器的参数综合。     

VLSI implementation of ART1 memories

A hardware implementation of long-term memory and short-term memory for binary input adaptive resonance theory (ART1) neural networks is presented. This implementation is based on chemical-electrical interactions in real neurons which are known to control axon release of chemical materials which in turn modulate the conductances of synapses. An axon-synapse-tree structure is introduced to achieve bottom-up long-term memory. The tree is realized by voltage modulation of synapse conductances. VLSI circuits are developed to realize the different functions of ART memories.     

A parallel processing VLSI BAM engine

In this paper emerging parallel/distributed architectures are explored for the digital VLSI implementation of adaptive bidirectional associative memory (BAM) neural network. A single instruction stream many data stream (SIMD)-based parallel processing architecture, is developed for the adaptive BAM neural network, taking advantage of the inherent parallelism in BAM. This novel neural processor architecture is named the sliding feeder BAM array processor (SLiFBAM). The SLiFBAM processor can be viewed as a two-stroke neural processing engine, It has four operating modes: learn pattern, evaluate pattern, read weight, and write weight. Design of a SLiFBAM VLSI processor chip is also described. By using 2-mum scalable CMOS technology, a SLiFBAM processor chip with 4+4 neurons and eight modules of 256x5 bit local weight-storage SRAM, was integrated on a 6.9x7.4 mm(2) prototype die. The system architecture is highly flexible and modular, enabling the construction of larger BAM networks of up to 252 neurons using multiple SLiFBAM chips.     

一种改进的低成本自适应双三次插值算法及VLSI实现

提出了一种新型图像缩放算法, 由自适应锐化滤波器和双三次插值组成.锐化滤波器减轻了双三次插值产生的模糊效应, 自适应技术进一步提升了图像缩放质量. 为了减少运算量, 提出前置滤波和后置滤波技术.与其他几种算法相比较, 本文的算法在主观和客观评价方面都明显胜出. 为了实现实时低成本设计, 提出了一种该算法的流水线超大规模集成电路 (Very large scale integration, VLSI)架构. 在现场可编程逻辑器件 (Field-programmable gate array, FPGA)上实现, 占用695个逻辑单元(Logic elements, LEs), 时钟频率达到165MHz, 减少了36.8%逻辑单元, 图像质量平均峰值信噪比 (Peak signal-to-noise ratio, PSNR)提升了1.5dB.     

Comparative implementations of the LMS algorithm

A study of available hardware algorithms was made in order to design adaptive signal processors with VLSI. A suitable model invoking synchrony, topology, and granularity has been chosen to investigate design figures-of-merit for each implementation. At present, redundant arithmetic is being contrasted, basically because carry-free operations are possible resulting in a speed up. This paper focuses on models and primitive computational elements for the least-mean-square (LMS) algorithm embedded in conventional twos complement, bit-serial or distributed arithmetic, and redundant arithmetic processors.     

Hardware implementation of adaptive feedback based reversible image watermarking for image processing application

This paper presents a reversible image watermarking (RIW) method including an adaptive feedback part based on difference expansion (DE). With respect to some parameters of the image, peak signal to noise ratio (PSNR), the highest payload capacity and the corresponding embedding threshold are spontaneously calculated by using the proposed adaptive feedback-based reversible Image watermarking (AFRIW). The payload capacity for data embedding is briefly explained. The machinery part of the adaptive feedback for controlling the payload capacity is presented. Software verification of three cover images is presented. Based on some image parameters, the comparative result between the proposed AFRIW algorithm and DE-based RIW method is presented. This paper also presents the VLSI architecture of this proposed algorithm for RIW. The proposed architecture has been implemented using VIVADO 2016.2 based on Xilinx Virtex-7 FPGA and Zynq device platforms. The software implementation results clearly demonstrated that the AFRIW method provides higher PSNR than the DE-based RIW method. The hardware implementation results indicate that the proposed algorithm has low timing complexity over other existing feedback based RIW algorithms which in turn provide higher speed.

     

谈VLSI在通信系统中的应用

研究VLSI在通信系统中的应用,讨论了实时数字信号处理的VLSI实现、CMOS的实现等问题,VLSI在通信系统的中的应用是提高通信质量和通信设备便携性的主要技术手段,是有望改变通信系统形式的核心技术。     

An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

In this paper, we propose an optimal VLSI implementation for a class of programmable FIR filters with binary coefficients, whose architecture is based on a parameterized divide and conquer approach. The proposed design is shown to be easily extendable to FIR filters with multibit coefficients of arbitrary sign. The area efficiency achieved in comparison to direct form realization is demonstrated by VLSI implementation examples, synthesized in TSMC 0.18-μm single poly six metal layer CMOS process using state-of-art VLSI EDA tools. The possible saving in average power consumption is estimated using gate-level power analysis. Suggestions for applications and topics for further research conclude the paper.     

Weight perturbation: an optimal architecture and learning techniquefor analog VLSI feedforward and recurrent multilayer networks

Previous work on analog VLSI implementation of multilayer perceptrons with on-chip learning has mainly targeted the implementation of algorithms such as back-propagation. Although back-propagation is efficient, its implementation in analog VLSI requires excessive computational hardware. It is shown that using gradient descent with direct approximation of the gradient instead of back-propagation is more economical for parallel analog implementations. It is shown that this technique (which is called ;weight perturbation') is suitable for multilayer recurrent networks as well. A discrete level analog implementation showing the training of an XOR network as an example is presented.