In situ nanomechanics of GaN nanowires

The deformation, fracture mechanisms, and the fracture strength of individual GaN nanowires were measured in real time using a transmission electron microscope-scanning probe microscope (TEM-SPM) platform. Surface mediated plasticity, such as dislocation nucleation from a free surface and plastic deformation between the SPM probe (the punch) and the nanowire contact surface were observed in situ. Although local plasticity was observed frequently, global plasticity was not observed, indicating the overall brittle nature of this material. Dislocation nucleation and propagation is a precursor before the fracture event, but the fracture surface shows brittle characteristic. The fracture surface is not straight but kinked at (10-10) or (10-11) planes. Dislocations are generated at a stress near the fracture strength of the nanowire, which ranges from 0.21 to 1.76 GPa. The results assess the mechanical properties of GaN nanowires and may provide important insight into the design of GaN nanowire devices for electronic and optoelectronic applications.     

Fabrication of suspended silicon nanowire arrays

A method to fabricate suspended silicon nanowires that are applicable to electronic and electromechanical nanowire devices is reported. The method allows for the wafer-level production of suspended silicon nanowires using anisotropic etching and thermal oxidation of single-crystal silicon. The deviation in width of the silicon nanowire bridges produced using the proposed method is evaluated. The NW field-effect transistor (FET) properties of the device obtained by transferring suspended nanowires are shown to be practical for useful functions.     

Silicidation of silicon nanowires by platinum

The solid-state reaction between platinum and silicon nanowires grown by the vapor-liquid-solid technique was studied. The reaction product PtSi is an attractive candidate for contacts to p-type silicon nanowires due to the low barrier height of PtSi contacts to p-type Si in the planar geometry, and the formation of PtSi was the motivation for our study. Silicidation was carried out by annealing Pt on Si nanowires from 250 to 700 degrees C, and the reaction products were characterized by transmission electron microscopy. Strikingly different morphologies of the reacted nanowires were observed depending on the annealing temperature, platinum film thickness, silicon nanowire diameter, and level of unintentional oxygen contamination in the annealing furnace. Conversion to PtSi was successfully realized by annealing above 400 degrees C in purified N2 gas. A uniform morphology was achieved for nanowires with an appropriate combination of Si nanowire diameter and Pt film thickness to form PtSi without excess Pt or Si. Similar to the planar silicidation process, oxygen affects the nanowire silicidation process greatly.     

Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.     

Device fabrication with solid-liquid-solid grown silicon nanowires

High quality, single-crystal silicon nanowires were successfully grown from silicon wafers with a nickel catalyst by utilizing a solid-liquid-solid (SLS) mechanism. The nanowires were composed of a crystalline silicon core with an average diameter of 10?nm and a thick outer oxide layer of between 20 and 30?nm at a growth temperature of 1000?°C. When utilizing the SLS growth mechanism, the diameter of the silicon nanowire is dependent solely upon the growth temperature, and has no relation to either the size or the shape of the catalyst. The characteristics of the silicon nanowires are highly dependent upon the properties of the silicon substrate, such as the crystal phase of silicon itself, as well as the doping type. The possibility of doping of silicon nanowires grown via the SLS mechanism without any external dopant source was demonstrated by measuring the electrical properties of a silicon nanowire field effect transistor.     

Single crystalline PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices

We report the formation of PtSi nanowires, PtSi/Si/PtSi nanowire heterostructures, and nanodevices from such heterostructures. Scanning electron microscopy studies show that silicon nanowires can be converted into PtSi nanowires through controlled reactions between lithographically defined platinum pads and silicon nanowires. High-resolution transmission electron microscopy studies show that PtSi/Si/PtSi heterostructure has an atomically sharp interface with epitaxial relationships of Si[110]//PtSi[010] and Si(111)//PtSi(101). Electrical measurements show that the pure PtSi nanowires have low resistivities approximately 28.6 microOmega.cm and high breakdown current densities>1x10(8) A/cm2. Furthermore, using single crystal PtSi/Si/PtSi nanowire heterostructures with atomically sharp interfaces, we have fabricated high-performance nanoscale field-effect transistors from intrinsic silicon nanowires, in which the source and drain contacts are defined by the metallic PtSi nanowire regions, and the gate length is defined by the Si nanowire region. Electrical measurements show nearly perfect p-channel enhancement mode transistor behavior with a normalized transconductance of 0.3 mS/microm, field-effect hole mobility of 168 cm2/V.s, and on/off ratio>10(7), demonstrating the best performing device from intrinsic silicon nanowires.     

Local electrode atom probe analysis of silicon nanowires grown with an aluminum catalyst

Local electrode atom probe (LEAP) tomography of Al-catalyzed silicon nanowires synthesized by the vapor–liquid–solid method is presented. The concentration of Al within the Al-catalyzed nanowire was found to be 2 × 10(20) cm(-3), which is higher than the expected solubility limit for Al in Si at the nanowire growth temperature of 550°C. Reconstructions of the Al contained within the nanowire indicate a denuded region adjacent to the Al catalyst/Si nanowire interface, while Al clusters are distributed throughout the rest of the silicon nanowire.     

化学蚀刻法制备纳米硅线作为高能锂离子电池的负极

采用金属催化剂诱导化学蚀刻法首先在单晶硅片上制备出具有高长径比的纳米硅线阵列, 然后通过超声振荡法将硅线阵列破碎为纳米硅线粉体, 最后将其作为锂离子电池的负极材料, 系统研究了金属银催化剂制备过程和各向异性化学蚀刻过程对硅片表面形貌特征的影响, 发现银催化剂在蚀刻过程出现溶解/再沉积现象。通过优化AgNO₃、HF、H₂O₂等试剂的浓度, 在大面积范围内得到了高长径比的纳米硅线阵列。借助超声波的作用将硅线从硅片上切割下来, 制备成纳米硅线负极进行了充放电循环测试, 观察到标准的硅锂合金/去合金化反应平台, 前五次循环的比容量均超过1800 mAh/g。     

Molecular dynamics evaluation of strain rate and size effects on mechanical properties of FCC nickel nanowires

Based on molecular dynamics method, an atomistic simulation scheme for damage evolution and failure process of nickel nanowires is presented, in which the inter-atomic interactions are represented by employing the modified embedded atom potential. Extremely high strain rate effect on the mechanical properties of nickel nanowires with different cross-sectional sizes is investigated. The stress–strain curves of nickel nanowires at different strain rates subjected to uniaxial tension are simulated. The elastic modulus, yield strength and fracture strength of nanowires at different loading cases are obtained, and the effect of strain rate on these mechanical properties is analyzed. The numerical results show that the stress–strain curve of metallic nanowires under tensile loading has the trend identical to that of routine polycrystalline metals, and the yield strain of nanowires is independent of the strain rate and cross-sectional size. Based on the simulation results, a set of quantitative prediction formulas are obtained to describe the strain rate sensitivity of nickel nanowires on the mechanical properties, and the resulting formulas of the Young’s modulus, yield strength and fracture strength of nickel nanowires exhibit a linear relation with respect to the logarithm of strain rate. Furthermore, some comprehensive correlation equations revealing both the strain rate and size effects on mechanical properties of nickel nanowire are proposed through the numerical fitting and regression analysis, and the mechanical behaviors observed in this study are consistent with those from the experimental and available numerical results.     

Nanowires for integrated multicolor nanophotonics

Nanoscale light-emitting diodes (nanoLEDs) with colors spanning from the ultraviolet to near-infrared region of the electromagnetic spectrum were prepared using a solution-based approach in which emissive electron-doped semiconductor nanowires were assembled with nonemissive hole-doped silicon nanowires in a crossed nanowire architecture. Single- and multicolor nanoLED devices and arrays were made with colors specified in a predictable way by the bandgaps of the III-V and II-VI nanowire building blocks. The approach was extended to combine nanoscale electronic and photonic devices into integrated structures, where a nanoscale transistor was used to switch the nanoLED on and off. In addition, this approach was generalized to hybrid devices consisting of nanowire emitters assembled on lithographically patterned planar silicon structures, which could provide a route for integrating photonic devices with conventional silicon microelectronics. Lastly, nanoLEDs were used to optically excite emissive molecules and nanoclusters, and hence could enable a range of integrated sensor/detection "chips" with multiplexed analysis capabilities.     

Selective surface functionalization of silicon nanowires via nanoscale joule heating

In this letter, we report a novel approach to selectively functionalize the surface of silicon nanowires located on silicon-based substrates. This method is based upon highly localized nanoscale Joule heating along silicon nanowires under an applied electrical bias. Numerical simulation shows that a high-temperature (>800 K) with a large thermal gradient can be achieved by applying an appropriate electrical bias across silicon nanowires. This localized heating effect can be utilized to selectively ablate a protective polymer layer from a region of the chosen silicon nanowire. The exposed surface, with proper postprocessing, becomes available for surface functionalization with chemical linker molecules, such as 3-mercaptopropyltrimethoxysilanes, while the surrounding area is still protected by the chemically inert polymer layer. This approach is successfully demonstrated on silicon nanowire arrays fabricated on SOI wafers and visualized by selective attachment of gold nanoparticles.     

Formation of Single Tiers of Bridging Silicon Nanowires for Transistor Applications Using Vapor–Liquid–Solid Growth from Short Silicon‐on‐Insulator Sidewalls

Single tiers of silicon nanowires that bridge the gap between the short sidewalls of silicon‐on‐insulator (SOI) source/drain pads are formed. The formation of a single tier of bridging nanowires is enabled by the attachment of a single tier of Au catalyst nanoparticles to short SOI sidewalls and the subsequent growth of epitaxial nanowires via the vapor–liquid–solid (VLS) process. The growth of unobstructed nanowire material occurs due to the attachment of catalyst nanoparticles on silicon surfaces and the removal of catalyst nanoparticles from the SOI‐buried oxide (BOX). Three‐terminal current–voltage measurements of the structure using the substrate as a planar backgate after VLS nanowire growth reveal transistor behaviour characteristics.     

Silicon nanowire transistors with a channel width of 4 nm fabricated by atomic force microscope nanolithography

The emergence of an ultrasensitive sensor technology based on silicon nanowires requires both the fabrication of nanoscale diameter wires and the integration with microelectronic processes. Here we demonstrate an atomic force microscopy lithography that enables the reproducible fabrication of complex single-crystalline silicon nanowire field-effect transistors with a high electrical performance. The nanowires have been carved from a silicon-on-insulator wafer by a combination of local oxidation processes with a force microscope and etching steps. We have fabricated and measured the electrical properties of a silicon nanowire transistor with a channel width of 4 nm. The flexibility of the nanofabrication process is illustrated by showing the electrical performance of two nanowire circuits with different geometries. The fabrication method is compatible with standard Si CMOS processing technologies and, therefore, can be used to develop a wide range of architectures and new microelectronic devices.     

Giant enhancement of the carrier mobility in silicon nanowires with diamond coating

We show theoretically that the low-field carrier mobility in silicon nanowires can be greatly enhanced by embedding the nanowires within a hard material such as diamond. The electron mobility in the cylindrical silicon nanowires with 4-nm diameter, which are coated with diamond, is 2 orders of magnitude higher at 10 K and a factor of 2 higher at room temperature than the mobility in a free-standing silicon nanowire. The importance of this result for the downscaled architectures and possible silicon-carbon nanoelectronic devices is augmented by an extra benefit of diamond, a superior heat conductor, for thermal management.     

Assessing charge carrier trapping in silicon nanowires using picosecond conductivity measurements

Free-standing semiconductor nanowires on bulk substrates are increasingly being explored as building blocks for novel optoelectronic devices such as tandem solar cells. Although carrier transport properties, such as mobility and trap densities, are essential for such applications, it has remained challenging to quantify these properties. Here, we report on a method that permits the direct, contact-free quantification of nanowire carrier diffusivity and trap densities in thin (～25 nm wide) silicon nanowires-without any additional processing steps such as transfer of wires onto a substrate. The approach relies on the very different terahertz (THz) conductivity response of photoinjected carriers within the silicon nanowires from those in the silicon substrate. This allows quantifying both the picosecond dynamics and the efficiency of charge carrier transport from the silicon nanowires into the silicon substrate. Varying the excitation density allows for quantification of nanowire trap densities: for sufficiently low excitation fluences the diffusion process stalls because the majority of charge carriers become trapped at nanowire surface defects. Using a model that includes these effects, we determine both the diffusion constant and the nanowire trap density. The trap density is found to be orders of magnitude larger than the charge carrier density that would be generated by AM1.5 sunlight.     

Fabrication and application of long silicon nanowire yarns

Long silicon nanowire yarns with length up to 12 mm were fabricated from aligned silicon nanowires with crystal silicon cores of bifurcation structures as well as entangled amorphous hairy silicon oxide, which played vital roles in the formation of the yarns, and the silicon nanowire yarns were used as a pH sensor with the sensitivity of 1,080 ± 31 nS/pH in the pH range of 2–12.     

Precise Alignment of Single Nanowires and Fabrication of Nanoelectromechanical Switch and Other Test Structures

The integration of nanowires and nanotubes into electrical test structures to investigate their nanoelectronic transport properties is a significant challenge. Here, we present a single nanowire manipulation system to precisely maneuver and align individual nanowires. We show that a single nanowire can be picked up and transferred to a predefined location by electrostatic force. Compatible fabrication processes have been developed to simultaneously pattern multiple aligned nanowires by using one level of photolithography. In addition, we have fabricated and characterized representative devices and test structures including nanoelectromechanical switches with large on/off current ratios, bottom-gated silicon nanowire field-effect transistors, and both transfer-length-method and Kelvin test structures     

Rate dependent deformation of a silicon nanowire under uniaxial compression: Yielding, buckling and constitutive description

This paper investigates the effect of compressive strain rate on the mechanical behaviour of single crystalline silicon nanowires using molecular dynamics simulation. It was found that of the whole range of the strain rates studied, the initial deformation of a nanowire is elastic. At lower strain rates the nanowire exhibits greater elasticity, and simple constitutive equations can be developed to describe the nanoscale structure and its deformation mechanism. With the increase in strain rate, the buckling stress increases and becomes steady at medium strain rates. On applying a very high strain rate, which is equivalent to a mechanical shock, the maximum buckling stress has a sudden rise and the silicon nanowire undergoes ballistic annihilation at both ends.     

镍间隙掺杂硅纳米线电子结构的研究

采用基于密度泛函理论的第一性原理的方法,对[100]方向镍间隙掺杂硅纳米线结构的稳定性和电子性质进行了计算。计算结果表明Ni原子更喜欢占据硅纳米线内部六角形间隙位置;掺杂体系费米能级附近的电子态密度来源于Ni3d态电子的贡献;同时发现不同构型的Ni掺杂硅纳米线,其带隙不同,且与未掺杂硅纳米线相比,带隙普遍减小。     

Integrated freestanding single-crystal silicon nanowires: conductivity and surface treatment

Integrated freestanding single-crystal silicon nanowires with typical dimension of 100 nm × 100 nm × 5 μm are fabricated by conventional 1:1 optical lithography and wet chemical silicon etching. The fabrication procedure can lead to wafer-scale integration of silicon nanowires in arrays. The measured electrical transport characteristics of the silicon nanowires covered with/without SiO(2) support a model of Fermi level pinning near the conduction band. The I-V curves of the nanowires reveal a current carrier polarity reversal depending on Si-SiO(2) and Si-H bonds on the nanowire surfaces.