A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier (VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB (-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

A 0.18μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio uitra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4-5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3-5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5-5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below-13 dB over 2.9-5.4 GHz. The input-referred 1-dB compression point (IPldB) is -11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.     

增益可调宽带CMOS低噪声放大器设计

设计了一种应用于超宽带系统中的可变增益宽带低噪声放大器。电路中采用了二阶巴特沃斯滤波器作为输入和输出匹配电路;采用了两级共源共栅结构实现电路的放大,并通过控制第二级的电流,实现了在宽频带范围内增益连续可调;采用了多栅管(MGTR),提高了电路的线性度;设计基于SMIC 0.18μm CMOS工艺。仿真结果显示,在频带3~5 GHz的范围内最高增益17 dB,增益波动小于1.8 dB,输入和输出端口反射系数分别小于-10 dB和-14 dB,噪声系数nf小于3.5 dB,当控制电压Vctrl=1.4 V时,IIP3约为2 dBm,电路功耗为16 mW。     

An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-$mu{hbox{m}}$ SiGe BiCMOS Technology

This paper demonstrates an 8-element phased array receiver in a standard 0.18-mum SiGe BiCMOS (1P6M, SiGe HBT f_t ap 150 GHz) technology for X- and Ku-band applications. The array receiver adopts the All-RF architecture, where the phase shifting and power combining are done at the RF level. With the integrations of all the digital control circuitry and ESD protection for all I/O pads, the receiver consumes a current of 100 ~ 200 m A from a 3.3 V supply voltage. The receiver shows 1.5 ~ 24.5 dB of power gain per channel from a 50 Omega load at 12 GHz with bias current control, and an associated NF of 4.2 dB (@ max. gain) to 13.2 dB (@ min. gain). The RMS gain error is < 0.9 dB and the RMS phase error is < 6deg at 6-18 GHz for all 4-bit phase states. The measured group delay is 162.5 plusmn 12.5 ps for all phase states at 6-18 GHz. The RMS phase mismatch and RMS gain mismatch among the eight channels are < 2.7deg and 0.4 dB, respectively, for all 16 phase states, over 6-18 GHz. The 8-element array can operate instantaneously at any center frequency and with a wide bandwidth (3 to 6 GHz, depending on the center frequency) given primarily by the 3 dB gain variation in the 6-18 GHz range. To our knowledge, this is the first demonstration of an All-RF phased array on a silicon chip with very low RMS phase and gain errors at 6-18 GHz. The chip size is 2.2 times 2.45 mm² including all pads.     

A Two Stage Variable-Gain Low-Noise Amplifier for X-Band in 0.18 µm CMOS

In this paper a variable gain low noise amplifier (VG-LNA) is designed and analyzed for X band in 0.18 µm CMOS technology. A two-stage structure is utilized in the proposed VG-LNA and its gain, which is controlled by an on-chip voltage (V_cnt), has continuous and almost linear variations. The required range for V_cnt can be initiated from 0.5 V, also the variations of gain doesn’t ruin reflection loss (S11), return loss (S12) and noise figure (NF). The best performance of this VG-LNA is at 10 GHz frequency with 1 GHz bandwidth. In the center frequency, the maximum gain is 20.8 dB that continuously and linearly decreases to 4 dB by increasing V_cnt. Also S11 and S12 in this frequency are lower than ?27 and ?38 dB, respectively. NF is lower than 2 dB in the mentioned frequency range and NF_min is equal to 1.2 dB, while the third-order intercept point (IIP3) equals to 8.27 dBm in the best condition and always stays above ?10 dBm. The main advantage of the proposed structure in compare with the similar structures is not only the key parameters don’t ruin by the gain variations, but also increment of V_cnt operation range (0.5 V to V_dd), leads to expanding gain control range. These results are achieved while the power consumption is 8.4 mW with 1.8 V supply voltage and the chip area is 0.56 mm².     

应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

8-GHz CMOS quadrature VCO using transformer-based LC tank

A fully integrated quadrature VCO at 8 GHz is presented. The VCO is implemented using a transformer-based LC tank in 0.18 /spl mu/m CMOS technology, in which two VCOs are coupled to generate I-Q signals. The VCO is realized employing the drain-gate transformer feedback configuration proposed here. This makes use of the quality factor enhancement in the resonator using a transformer and the deep switching-off technique by controlling gate bias. By turning off switching transistors of the differential VCO core deeply, the phase noise performance is improved more than 10 dB. The measured phase noise values are -110 and -117 dBc/HZ at the offset frequencies of 600 kHz and 1 MHz respectively. The tuning range of 250 MHz is achieved with the control voltage from 0 to 1 V. The VCO draws 8 mA in two differential core circuits from 3 V supply. When the bias voltage goes down to 2.5 V, the phase noise decrease only 2 dB compared to that of 3 V bias. The VCO performances are compared with previously reported quadrature Si VCOs in 5/spl sim/12 GHz frequency range.     

2.5 dB NF 3.1-10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1-10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only plusmn 16.7 ps across the whole band) using standard 0.13 mum CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S₁₁) of -17.5 to -33.6 dB, output return loss (S₂₂) of -14.4 to -16.3 dB, flat forward gain (S₂₂) of 7.92 plusmn 0.23 dB, and reverse isolation (S₁₂) of -25.8 to -41.9 dB over the 3.1-10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.     

A monolithic DC temperature compensation bias scheme for multistageHEMT integrated circuits

This work benchmarks the first demonstration of a multistage monolithic HEMT IC design which incorporates a DC temperature compensated current-mirror bias scheme. This is believed to be the first demonstrated monolithic HEMT bias scheme of its kind. The active bias approach has been applied to a 2-18 GHz five-section low noise HEMT distributed amplifier which achieves a nominal gain of 12.5 dB and a noise figure <2.5 dB across a 2-18 GHz band, The regulated current-mirror scheme achieves better than 0.2% current regulation over a 0-125°C temperature range, The RF gain response was also measured over the same temperature range and showed less than 0.75 dB gain degradation. This results in a -0.006 dB/°C temperature coefficient which is strictly due to HEMT device G_m variation with temperature. The regulated current-mirror circuit can be employed as a stand-alone V_gs-voltage reference circuit which fan be monolithically applied to the gate bias terminal of existing HEMT ICs for providing temperature compensated performance, This monolithic bias approach provides a practical solution to DC bias regulation and temperature compensation for HEMT MMICs which can improve the performance, reliability, and cost of integrated microwave assemblies (IMAs) used in space-flight military applications     

微波毫米波宽带单片低噪声放大器

推导了反馈电路理论,利用0.25μmGaAs PHEMT工艺,研制了两种并联反馈单片低噪声放大器。第一种放大器的工作频带为6～18GHz,测得增益G≥21dB,带内增益波动ΔG≤±1.0dB,噪声系数NF典型值为2.0dB,输入驻波VSWRin≤1.5,输出驻波VSWRout≤2.0,1分贝压缩点输出功率P1dB≥11dBm。第二种放大器的工作频带为26～40GHz,测得增益G≥17dB,噪声系数NF约为2.0dB,输入、输出驻波VSWR≤2.5,1分贝压缩点输出功率P1dB≥10dBm。两种电路的测试结果验证了设计的正确性。     

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-$mu$ m SiGe BiCMOS Technology

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P_-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm².     

一款130～140GHz MMIC低噪声放大器

基于90 nm栅长的InP高电子迁移率晶体管(HEMT)工艺,研制了一款工作于130 ～140 GHz的MMIC低噪声放大器(LNA).该款放大器采用三级级联的双电源拓扑结构,第一级电路在确保较低的输入回波损耗的同时优化了放大器的噪声,后两级则采用最大增益的匹配方式,保证了放大器具有良好的增益平坦度和较小的输出回波损耗.在片测试结果表明,在栅、漏极偏置电压分别为-0.25 V和3V的工作条件下,该放大器在130～ 140 GHz工作频带内噪声系数小于6.5 dB,增益为18 dB±1.5 dB,输入电压驻波比小于2:1,输出电压驻波比小于3:1.芯片面积为1.70 mm×1.10 mm.该低噪声放大器有望应用于D波段的收发系统中.     

应用于S波段的高线性低噪声放大器

采用E-mode 0.25um GaAs pHEMT工艺,2.0mm × 2.0mm 8-pin双侧引脚扁平封装,设计了一款应用于S波段的噪声系数低于0.5dB的低噪声放大器。通过采用共源共栅结构、有源偏置网络和多重反馈网络等技术改进了电路结构,该放大器具有低噪声,高增益,高线性等特点,是手持终端应用上理想的一款低噪声放大器。测试结果表明在2.3-2.7GHz内,增益大于18dB,输入回波损耗小于-10dB,输出回波损耗小于-16dB,输出三阶交调点大于36dB。     

Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends

Single-ended and differential phased array front-ends are developed for Ka-band applications using a 0.12 mum SiGe BiCMOS process. The phase shifters are based on CMOS switched delay networks and have 22.5deg phase resolution and <4deg rms phase error at 35 GHz, and can handle +10 dBm of RF power (P_1dB) with a 3rd order intermodulation intercept point (IIP3) of +21 dBm. For the single-ended design, a SiGe low noise amplifier is placed before the CMOS phase shifter, and the LNA/phase shifter results in 11 plusmn 1.5 dB gain and <3.4 dB of noise figure (NF), for a total power consumption of only 11 mW. For the differential front-end, a variable gain LNA is also developed and shows 9-20 dB gain and <1deg rms phase imbalance between the eight different gain states. The differential variable gain LNA/phase shifter consumes 33 mW, and results in 10 + 1.3 dB gain and 3.8 dB of NF. The gain variation is reduced to 9.1 plusmn 0.45 dB with the variable gain function applied. The single-ended and differential front-ends occupy a small chip area, with a size of 350 times 800 mum² and 350 times 950 mum2, respectively, excluding pads. These chips are competitive with GaAs and InP designs, and are building blocks for low-cost millimeter-wave phased array front-ends based on silicon technology.     

A 2.5-GHz InGaP/GaAs differential cross-coupled self-oscillating mixer (SOM) IC

This letter presents a monolithic differential cross-coupled self-oscillating mixer (SOM). The SOM chip is fabricated using an InGaP/GaAs heterojunction bipolar transistor (HBT) foundry process and operates at 2.5 GHz. The chip provides voltage controlled oscillator (VCO) operation, up- and down-conversion mixing, and injection locking functionalities. The voltage down-conversion gain and the power up-conversion gain of up to 15 and 11.5 dB, respectively, are measured for the circuit. There is a compromise between obtaining a high conversion gain, and the oscillator power (-0.3 dBm for a 5-V supply) and phase noise (-84 dBc/Hz at 100 kHz). However, phase noise improvement of 32dB is observed by injection of a -30-dBm stable reference.     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

5～10 GHz MMIC低噪声放大器

采用稳懋公司150 nm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,设计了一款5 ～ 10 GHz单片微波集成电路(MMIC)低噪声放大器(LNA).该LNA采用三级级联结构,且每一级采用相同的偏压条件,电路的低频工作端依靠电容反馈,高频工作端依靠电阻反馈调节阻抗匹配,从而实现宽带匹配,芯片面积为2.5 mm×1 mm.测试结果表明,工作频率为5～10 GHz,漏极电压为2.3V,工作电流为70 mA时,LNA的功率增益达到35 dB,平均噪声温度为82 K,在90％工作频段内输入输出回波损耗优于-15 dB,1 dB压缩点输出功率为10.3 dBm,仿真结果与实验结果具有很好的一致性.     

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.