共查询到19条相似文献,搜索用时 31 毫秒
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本文着重介绍了下一代处理器Merced的IA-64结构所采用的推断技术和风险装栽技术。并对处理器前途作简要评述。 相似文献
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Jim Harrison 《今日电子》2006,(3):33-33
P.A.Semi(Santa Clara,美国加州)公司准备发布一款高性能的64位处理器,据称可以在同样性能的水平下,将功耗降低到目前产品的1/10。PA6T-1682M通过采用新的架构设计、工艺的改进和先进的时钟管理技术来实现低功耗,芯片上的门控时钟多达15000个。 相似文献
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64位MIPS指令处理器的流水线设计 总被引:2,自引:1,他引:1
介绍了一种采用64位MIPS指令集CPU的流水线设计。作为SOC的核心,CPU的性能主要取决于指令的执行效率,而采用流水线方式大大增加了指令的执行速度,提高了CPU的性能。该CPU使用五级流水线设计,文中对影响流水线正常执行的各种因素进行了分析,以及在实际设计中采用相应的控制机制,从而完成对一个具有较高性能的CPU核的流水线控制的设计。 相似文献
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《Solid-State Circuits, IEEE Journal of》1984,19(4):538-539
A double/single-precision floating-point processor using a titanium disilicide 3.5-/spl mu/m NMOS process achieves double-precision add/subtract, multiply, and divide in 2, 8, and 16 /spl mu/s respectively. The chip has about 35K devices and is about 400 mil on the side. The chip uses a single 5-V supply with TTL-compatible levels on all signals except for the clocks, which require 4.5 V for a logic high. Four input clocks are used to generate eight 50-ns intervals. A -2.5 V substrate bias generator is designed on the chip but uses a pin for an external capacitor. The processor, which is to be used in a desktop implementation of a minicomputer, executes the floating-point instruction set for the micro-Eclipse computer. 相似文献
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《Solid-State Circuits, IEEE Journal of》1982,17(5):898-907
Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems. 相似文献
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Silberman J. Aoki N. Boerstler D. Burns J.L. Sang Dhong Essbaum A. Ghoshal U. Heidel D. Hofstee P. Kyung Tek Lee Meltzer D. Hung Ngo Nowka K. Posluszny S. Takahashi O. Vo I. Zoric B. 《Solid-State Circuits, IEEE Journal of》1998,33(11):1600-1608
The organization and circuit design of a 1.0 GHz integer processor built in 0.25 μm CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented 相似文献
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Benschneider B.J. Bowhill W.J. Copper E.M. Gavrielov M.N. Gronowski P.E. Maheshwari V.K. Peng V. Pickholtz J.D. Samudrala S. 《Solid-State Circuits, IEEE Journal of》1989,24(5):1317-1323
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.<> 相似文献
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一种64位高速PCI总线接口的设计与实现 总被引:3,自引:1,他引:3
设计了一种基于PCI9656的高速PCI总线接口,数据传输主要为DMA方式。文中介绍了PCI9656的内部结构和功能,讨论了其WDM驱动开发过程,分析了其局部总线在进行DMA传输时的配置时序,提出了一些设计中需要注意的问题。实际应用结果表明,该总线接口性能稳定且优良,可以应用于高速数据传输系统。 相似文献
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BC7280/818位/16位LED数码管显示及64键键盘控制芯片的特点和应用 总被引:1,自引:1,他引:0
BC7280/81是比高公司推出的8位/16位LED数码管显示及键盘接口专用控制芯片,可用于控制16位数码管或128只独立的LED。文中介绍了BC7280/81的主要特点,引脚功能,主要参数及接口时序,给出了它的典型应用电路和汇编语言程序。 相似文献