64位处理器

今天大多数计算机采用的是32位处理器(诸如Intel的Pentium),运行32位操作系统(包括Windows XP、Mac OS、Unix和Linux).回溯以往,计算机曾用过8位微处理器(如Zilog Z80),然后迎来了16位芯片(Intel 8086和Motorola 68000).     

64位处理器IA—64的技术特点

本文着重介绍了下一代处理器Ｍｅｒｃｅｄ的ＩＡ－６４结构所采用的推断技术和风险装栽技术。并对处理器前途作简要评述。     

64位处理器Cortex-A50系列

ARM公司的新款ARM v8架构ARM CortexTM-A50处理器系列产品,率先推出的是Cortex-A53与Cortex-A57处理器以及最新节能64位处理技术与现有32位处理技术的扩展升级。Cortex-A57是ARM最先进、性能最高的应用处理器,而Cortex-A53不仅是功耗效率最高的ARM应用处理器,也是全球最小的64位处理器。这两款处理器可各自独立运作或整合为ARM big.LITTLETM处理器架构,     

IDT提供64位元处理器

Integrated Device Technology,Inc.(IDT)宣布推出新一代的R50O0 MPS RISC微处理器。这是IDT首次开发出的Superscalar处理器,使得在嵌入式应用上可以达到前所未有的性能。R5000在视像运算上提供卓越的图像功能,而在网际网路应用上,则能提供更高的频宽。     

大幅降低功耗的高性能64位处理器

P．A．Semi（Santa Clara,美国加州）公司准备发布一款高性能的64位处理器,据称可以在同样性能的水平下,将功耗降低到目前产品的1／10。PA6T-1682M通过采用新的架构设计、工艺的改进和先进的时钟管理技术来实现低功耗,芯片上的门控时钟多达15000个。     

64位移动计算

在笔记本电脑领域，除了迅驰之外，64位移动计算技术便是另一个无可非议的热点话题，虽然早在2003年英特尔（Intel）公司便宣布全面支持该技术并发布了几款64位台式处理器。     

用于个人电脑的AMD Athlon 64位处理器

今年4月,AMD推出用于服务器及工作站的AMD Opteron处理器,将64位计算能力推向市场。9月,AMD再次推出用于台式机及笔记本电脑的AMD Athlon 64位处理器,型号为AMD Athlon 64 FX处理器是目前业界最先进、性能最高,并且可同时支持32位及64位计算的个人电脑处理器。 AMD 64技术是在业内标准x86     

64位MIPS指令处理器的流水线设计

介绍了一种采用64位MIPS指令集CPU的流水线设计。作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。该CPU使用五级流水线设计，文中对影响流水线正常执行的各种因素进行了分析，以及在实际设计中采用相应的控制机制，从而完成对一个具有较高性能的CPU核的流水线控制的设计。     

64位处理器将奏响新世纪PC主旋律

<正> 2000年家用电脑市场最热眼的是什么?稍稍关注电脑发展的人士都会脱口而出:时尚、一键上网。 那么,2001年的电脑市场热点又会出现在哪里呢?从目前的市场动向看,众多电脑商家除了将继续演绎时尚、一键上网外,64位处理器可能要在高端PC市场一鸣惊人,成为一颗引人注目的耀眼新星。 毫无疑问,CPU是电脑的心脏,也是大家最为关心的配件。正是它确定了个人电脑的基本构架。但从386开始,桌面PC使用的CPU,包括最新推出的Pentium Ⅳ都还是32位构架的,而今64位处理器将不再是服务器的专利,并将在2001年脱颖而出。预计不久,高端产品将是64位处理器的天下,由此引发新一轮的市场竞争。     

A monolithic 64 bit floating-point coprocessor

A double/single-precision floating-point processor using a titanium disilicide 3.5-/spl mu/m NMOS process achieves double-precision add/subtract, multiply, and divide in 2, 8, and 16 /spl mu/s respectively. The chip has about 35K devices and is about 400 mil on the side. The chip uses a single 5-V supply with TTL-compatible levels on all signals except for the clocks, which require 4.5 V for a logic high. Four input clocks are used to generate eight 50-ns intervals. A -2.5 V substrate bias generator is designed on the chip but uses a pin for an external capacitor. The processor, which is to be used in a desktop implementation of a minicomputer, executes the floating-point instruction set for the micro-Eclipse computer.     

64 bit monolithic floating point processors

Describes a set of three processor chips capable of performing 32 and 64 bit floating point add/subtract, multiply, and divide operations. The chips can perform over one million scalar floating point operations per second, and over four million vector operations per second. The set is implemented in a four micron CMOS-on-sapphire process. Each chip has between 30000 and 60000 devices, and is about 250 mils on a side. Although asynchronous data paths are used within the chips, their interface to external system buses is synchronous with a maximum data bandwidth of over 70 Mbytes/s. The set has been designed for use in Hewlett-Packard computer and instrument systems.     

A 1.0-GHz single-issue 64-bit powerPC integer processor

The organization and circuit design of a 1.0 GHz integer processor built in 0.25 μm CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented     

A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed.<>     

BC7280/818位/16位LED数码管显示及64键键盘控制芯片的特点和应用

BC7280/81是比高公司推出的8位/16位LED数码管显示及键盘接口专用控制芯片，可用于控制16位数码管或128只独立的LED。文中介绍了BC7280/81的主要特点，引脚功能，主要参数及接口时序，给出了它的典型应用电路和汇编语言程序。     

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage