A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

A 0.7-7 GHz wideband reconfigurable receiver RF front-end in CMOS

In this paper,a 0.7-7 GHz wideband RF receiver front-end SoC is designed using the CMOS process.The front-end is composed of two main blocks:a single-ended wideband low noise amplifier (LNA) and an inphase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers.Based on a self-biased resistive negative feedback topology,the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth.The passive down-conversion mixer includes two parts:passive switches and IF amplifiers.The measurement results show that the front-end works well at different LO frequencies,and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency.The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB,a minimum noise figure (NF) of 3.2 dB,with an IF bandwidth of greater than 500 MHz.The chip area is 1.67 × 1.08 mm2.     

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

一种片上变压器为负载的用于0.13 μm CMOS工艺2.4GHz WLAN的接收机射频前端电路

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μ m CMOS technology, it occupies a 0.612 mm² die size.     

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed.It contains a differential transconductance low noise amplifier（G_m-LNA） and a differential current-mode 0 down converted mixer.The single terminal of the G_m-LNA contains just one MOS transistor,two capacitors and two inductors.The gate-source shunt capacitors,C_x1 and C_x2,can not only reduce the effects of gate-source C_gs on resonance frequency and input-matching impedance,but they also enable the gate inductance L_g1,2 to be selected at a very small value.The current-mode mixer is composed of four switched current mirrors.Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end.The RF front-end operates under 1 V supply voltage.The receiver RFIC was fabricated using a chartered 0.18μm CMOS process.The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point（IIP3） of-7.02 dBm.The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control(AGC) scheme and a digitally controlled radio frequency varied gain amplifier(RFVGA) for a U/V band China Mobile Multimedia Broadcasting(CMMB) direct conversion receiver.The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal,which is of importance for CMMB application.The front-end,composed of a low noise amplifier(LNA),an RFVGA,a mixer and AGC,achieves an input referred 3rd order intercept point(IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode,and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode.The proposed RF front-end is fabricated in a 0.35μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

A 0.35μm CMOS Mixer for 2.45-GHz RFID Application

A RF mixer with both low noise and high linearity is designed,operating at 2.45-GHz ISM band for RFID application.The designed mixer uses an optimal input matching network and the carefully chosen sizes of transistors,also with the appropriate bias point,to improve the noise figure(NF).Also,with a resonant LC loop as the current source and a parallel PMOS-resistor as the load,the mixer has a high linearity.The post simulation results show that the single side- band noise figure of 8.57 dB,conversion gain of 10.02 dB,input 1-dB compression point(P-1dB)of-8.33 dBm,and input third-order intercept point(IIP3)of 5.35 dBm.     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

应用于2.4GHz无线传感网的超低功耗射频接收前端设计

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.     

A low power high gain gain-controlled LNAC＋mixer for GNSS receivers

A low power high gain gain-controlled LNAC+mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load.Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNACmixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNAC+mixer, a previous low power LNAC+mixer, and the proposed LNAC+mixer are presented. The circuit is implemented in 0.18 m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2and consumes 2 mA current under 1.8 V supply.     

Research on optimizing the noise figure of low noise amplifier method via bias and frequency

In this paper,we present the design of an integrated low noise amplifier(LNA)for wireless local area network(WLAN)applications in the 5.15-5.825 GHz range using a SiGe BiCMOS technology.A novel method that can determine both the optimum bias point and the frequency point for achieving the minimum noise figure is put forward.The method can be used to determine the optimum impedance over a relevant wider operating frequency range.The results show that this kind of optimizing method is more suitable for the WLAN circuits design.The LNA gain is optimized and the noise figure(NF)is reduced.This method can also achieve the noise match and power match simultaneously.This proposal is applied on designing a LNA for IEEE 802.11a WLAN.The LNA exhibits a power gain large than 16 dB from 5.15 to 5.825 GHz range.The noise figure is lower than 2 dB.The OIP3 is 8 dBm.Also the LNA is matched to 50 Ω input impedance with 6 mA DC current for differential design.