莱斯信道下大规模MIMO系统混合模数转换器的随机向量量化方案

针对大规模MIMO系统用配置单精度模数转换器(ADC)来降低系统能耗会导致系统损失部分性能的问题,提出了一种莱斯信道下大规模MIMO系统的采用混合ADC的随机向量量化(RVQ)改进方案。该方案在频分双工模式下,首先在基站端采用高分辨率ADC和低分辨率ADC混合的接收方案处理信号,使接收的导频信号和有用信号具有较高的转换精度;系统对导频信号进行信道估计后,再对信道状态信息(CSI)进行RVQ处理,以此减小系统的反馈开销;最后运用最小均方误差(MMSE)信号检测算法减轻由量化误差引起的的用户间干扰,从而达到降低能耗并减小系统性能损失的目的。实验结果表明,这种改进的RVQ方案能在降低系统能耗的基础上有效减小系统容量损失,并使其和速率接近传统的高分辨率ADC接收方案。     

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

A new method for reducing DNL in nuclear ADCs using an interpolation technique

The paper describes a new method for reducing the DNL associated with nuclear ADCs. The method named the “interpolation technique” is utilized to derive the quantisation steps corresponding to the last n bits of the digital code by dividing quantisation steps due to higher significant bits of the DAC, using a chain of resistors. Using comparators, these quantisation steps are compared with the analog voltage to be digitized, which is applied as a voltage shift at both ends of this chain. The output states of the comparators define the n bit code. The errors due to offset voltages and bias currents of the comparators are statistically neutralized by changing the polarity of quantisation steps as well as the polarity of analog voltage corresponding to last n bits) for alternate A/D conversion. The effect of averaging on the channel profile can be minimized. A 12 bit ADC was constructured using this technique which gives DNL of less than ±1% over most of the channels for conversion time of nearly 4.5 μs. Gatti's sliding scale technique can be implemented for further reduction of DNL. The interpolation technique has a promising potential of improving the resolution of existing 12 bit ADCs to 16 bit, without degrading the percentage DNL significantly.     

A Digitally Programmable A/D Converter for Smart Sensors Applications

Nonlinear analog-to-digital conversion in smart sensor applications is an important topic since signal digitization and linearization can be performed in a single step near the transducer. In this paper a double pulsewidth modulated (PWM) scheme for nonlinear analog-to-digital conversion is presented. Calibration or auto-calibration data stored in the smart sensor's memory define the nonlinear profile characteristic of the transducer and provide the required data to obtain the inverse function of the analog-to-digital converter (ADC) transfer curve. Basically, as a function of the transducer's nonlinearity degree, the input voltage range of the ADC is segmented in a continuous set of subintervals and, for each of these subintervals, a second-order correction term based on a PWM A/D conversion is used to obtain a linear characteristic for the smart sensor. Additional advantages of this method result from its easy implementation in low-cost microcontrollers that include generally comparator inputs and PWM outputs. A flexible and programmable A/D conversion solution can be dynamically adapted to variations of the transducer's nonlinearity profile, and an increased resolution can be achieved at the expense of a lower conversion rate. Some MATLAB simulations and experimental results obtained with a square-root airflow transducer will be presented in the final part of the paper     

A 1-Ms/s 16-bit analog-to-digital converter

The author describes a 1-Ms/s. 16-bit analog-to-digital converter (ADC) that uses a subranging conversion technique. High accuracy at 1-MHz conversion rate is obtained with novel circuits developed for a track-and-hold (T/H), a residue amplifier, and a digital-to-analog converter (DAC). Design aspects of these key functional circuits are presented. A prototype ADC was fabricated on a PC board and tested. The results of curve fit tests show that, up to 100 kHz, effective bits are better than 16. However, signal bandwidth is commonly restricted in spectrum analysis; therefore, a dynamic range of over 96 dB can be obtained     

Instantaneous phase method for readout signal processing of body dithered ring laser gyro

The readout signal of a body dithered ring laser gyro contains both useful information and the dither component. The dither component must be removed to get the useful information. The dither stripping method can get the useful information without latency. But the quadrature demodulator only has 1/4 pulse resolution, which means that the quantization noise will limit the short-term accuracy. The effect and the property of quantization noise are analyzed in detail. Taking advantage of high-speed analog-to-digital conversion (ADC), the analog values of the two beat frequency signals in quadrature are sampled. A novel instantaneous phase method is introduced, which can get the residual phase besides 4× resolution and the quantization noise can be removed radically. The Allan variance analysis of experimental results shows that the quantization noise coefficient using this method is only 1/7 of that using the original 4× resolution method.     

Miniaturization of sensors and influence of their thermal noise onmeasurement accuracy

The influence of thermal fluctuations in the mechanical and electrical elements of microsensors on their measurement accuracy is considered. The limits of the minimum attainable measurement uncertainty as a function of the miniaturization degree of the sensor are evaluated. Possibilities of improvement of the sensor performance through optimal fitting of the sensor and ADC parameters are examined. Recommendations for an optimal choice of parameters of the analog part of the sensor as well of the ADC resolution are given. The analysis is based on the information-energetic theory of measurements, and on general results of statistical physics     

Improvement in the linearity of fast digital oscilloscopes used inaveraging mode

Accurate measurement of signals with very fast variations between values separated by several orders of magnitude is difficult. When signals are periodical, a fast digital oscilloscope may be used in averaging mode, but the measurement accuracy is mainly limited by analog-to-digital conversion (ADC) nonlinearity. In this paper, several methods for improving the conversion linearity are proposed. These methods are theoretically justified and experimentally validated. Several of these methods may be used simultaneously by an 8-bit digital oscilloscope to provide, in averaging mode, the linearity of an 11- or 12-bit ADC     

A new method for high speed nuclear ADCs using commercially available ADCs and DACs

This paper describes a new and simple method for high speed nuclear ADCs using commercially available high speed ADCs and monolithic DACs. The digital code corresponding to the input analog voltage, which is first determined with an accuracy of $\text{±}\text{1}\text{2}$ LSB using a commercial ADC (conversion time 2.5 μs), is corrected using a corrected monolithic DAC and external comparators to yield a DNL of better than ± 2% (without Gatti's scheme) with a total conversion time of 3.5 μs. The advantage of the method is the smaller size of the circuit and higher speed of operation compared with other methods. The recent improvements in speed, size and cost of commercial ($\text{±}\text{1}\text{2}\text{LSB}$) ADCs are directly utilized to improve the corresponding factors in nuclear ADCs. Use of Gatti's sliding scheme can further reduce the DNL to 0.2%.     

Statistical treatment of photon/electron counting: extending the linear dynamic range from the dark count rate to saturation

An experimentally simple photon counting method is demonstrated providing 7 orders of magnitude in linear dynamic range (LDR) for a single photomultiplier tube (PMT) detector. In conventional photon/electron counting methods, the linear range is dictated by the agreement between the binomially distributed measurement of counted events and the underlying Poisson distribution of photons/electrons. By explicitly considering the log-normal probability distribution in voltage transients as a function of the number of photons present and the Poisson distribution of photons, observed counts for a given threshold can be related to the mean number of photons well beyond the conventional limit. Analytical expressions are derived relating counts and photons that extend the linear range to an average of ～11 photons arriving simultaneously with a single threshold. These expressions can be evaluated numerically for multiple thresholds extending the linear range to the saturation point of the PMT. The peak voltage distributions are experimentally shown to follow a Poisson weighted sum of log-normal distributions that can all be derived from the single photoelectron voltage peak-height distribution. The LDR that results from this method is compared to conventional single photon counting (SPC) and to signal averaging by analog to digital conversion (ADC).     

A new ADC circuit for nuclear spectroscopy based on digital signal processing techniques

A 12-bit analog-to-digital converter (ADC) circuit for nuclear spectroscopy applications was developed using a digital signal processor (DSP) as the central processing element.

The DSP runs a program that builds the distribution function of data collected by the ADC (the multichannel analyzer algorithm) and simultaneously corrects the ADC differential nonlinearity (DNL) by the sliding scale method. The acquisition routine runs in 4 μs.

The conversion time, when the faster versions of the ADC are used, is well below 10 μs. The resulting DNL is better than 0.4% and the integral nonlinearity <0.002%.     

Ethernet-Based DAQ System for QUIET-II Detectors

The B-modes in cosmic microwave background polarization are a smoking gun for the inflationary universe. For the detection of the B-modes, having a large detector array is a generic approach since the B-modes is so faint pattern (T _b?0.1?μK). The Q/U Imaging ExperimenT Phase-II (QUIET-II) is proposed to search the B-modes, using an array with 500 HEMT-based polarimeters. Each polarimeter element has 4-outputs, therefore we have to manage 2000 channels in total. We developed a scalable DAQ system based on TCP/Ethernet for QUIET-II. The DAQ system is composed of the polarimeters, ADC boards, a Master Clock and a control computer (PC). The analog signals from the polarimeters are digitized on the ADC boards. On-board demodulation, which synchronizes the phase flip modulations on the polarimeter, extracts the polarized components in the digitized signal. The Master Clock distributes all necessary clocks to the ADC boards as well as the polarimeters. This scheme guarantees the synchronization of the modulations and demodulations. We employed Ethernet-based communication scheme between the data collection program (Collector) on the PC and the ADC boards as well as the Master Clock. Such an Ethernet-based communication scheme allows us to construct a simple structure of the upper level software, which results in the high scalability to increase the number of channels. All basic functions and requirements are confirmed by the laboratory tests; demonstration with test signals as well as the signals from the polarimeters, measurements of the data transfer rate, and the synchronous operation with two ADC boards. Therefore, the DAQ system is confirmed to be suitable for QUIET-II.     

Oscillation-test methodology for low-cost testing of active analogfilters

The oscillation-test strategy is a low cost and robust test method for mixed-signal integrated circuits. Being a vectorless test method, it allows one to eliminate the analog test vector generator. Furthermore, as the oscillation frequency is considered to be digital, it can be precisely analyzed using pure digital circuitry and can be easily interfaced to test techniques dedicated to the digital part of the circuit under test (CUT). This paper describes the design for testability (DFT) of active analog filters based on oscillation-test methodology. Active filters are transformed to oscillators using very simple techniques. The tolerance band of the oscillation frequency is determined by a Monte Carlo analysis taking into account the nominal tolerance of all circuit under test components. Discrete practical realizations and extensive simulations based on CMOS 1.2 μm technology parameters affirm that the test technique presented for active analog filters ensures high fault coverage and requires a negligible area overhead. Finally, the DFT techniques investigated are very suitable for automatic testable filter synthesis and can be easily integrated in the tools dedicated to automatic filter design     

PI controller scheme for charge balance in implantable electrical stimulators

Electrical stimulation has been used in a wide variety of medical implant applications. In all of these applications, due to safety concerns, maintaining charge balance becomes a critically important issue that needs to be addressed at the design stage. It is important that charge balancing schemes be robust to circuit (process) and load impedance variations, and at the same time must also lend themselves to miniaturization. In this communication, simulation studies on the effectiveness of using Proportional Integral (P-I) control schemes for managing charge balance in electrical stimulation are presented. The adaptation of the P-I control scheme to implant circuits leads to two possible circuit realizations in the analog domain. The governing equations for these realizations are approximated to simple linear equations. Considering typical circuit and tissue parameter values and their expected uncertainties, Matlab as well as circuit simulations have been carried out. Simulation results presented indicate that the tissue voltages settle to well below 20% of the safe levels and within about 20 stimulations cycles, thus confirming the validity and robustness of the proposed schemes.     

Analysis of the resolution-bandwidth-noise trade-off in wavelength-based photonic analog-to-digital converters

The performance of wavelength-based photonic analog-to-digital converters (ADCs) is theoretically analyzed in terms of resolution and bandwidth as well as of noise tolerance. The analysis applies to any photonic ADC in which the analog input signal is converted into the wavelength of an optical carrier, but special emphasis is put on the spectrometerlike setup in which the wavelength is mapped to a spatial spot position. The binary output signals are then retrieved by an array of fan-out diffractive optical elements that redirect the beam onto the correct detectors. In particular, the case when the input signal controls the wavelength directly such that it will chirp in frequency during each sampling pulse or interval is studied. This chirping obviously broadens the spot on the diffractive optical element array; the effect of this broadening on noise tolerance and comparator accuracy is analytically analyzed, and accurate numerical calculations of the probability of error are presented.     

A Time-Domain Comparator Based Skipping-Window SAR ADC

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator, which can provide not only the polarity of the input, but also the amount information of the input. The time-domain comparator, which is based on the edge pursing principle, consists of delay cells, two NAND gates, two D-flip-flop register-based phase detectors and a counter. The digital characteristic of the comparator makes the design more flexible, and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number. An energy efficient digital-to-analog converter (DAC) control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion. Together with the skipping-window technique, the linearity and the power consumption of the SAR ADC are improved. The impact of different window sizes on comparison cycles, DAC switching energy and the overall energy efficiency is analyzed. Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC, as well as the linearity, and the optimized window size for the overall energy efficiency will vary with the DAC switching energy.     

Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement

Timing measurements for gigahertz clock frequencies require high accuracy and resolution. This paper proposes a scalable built-in self-test (BIST) method that measures accumulated period jitter over a programmable number of periods, without using another reference clock. This on-chip method uses a charge pump to convert time to a voltage, which is digitized by an all-digital flash analog-to-digital converter (ADC). The ADC employs multiple chains of inverter strings composed of three series inverters instead of the popular analog comparators. The inverter thresholds set the reference voltages for triggering given an input dc value. The output is calibrated and converted to jitter measurement. The design using a 0.25 /spl mu/m BiCMOS process, with an input range of 625 MHz-1 GHz, shows that a resolution of 70 ps root mean square (rms) jitter can be achieved, while occupying 0.0575 mm/sup 2/ area with a very conservative layout style. The design has been fabricated and tested, and the test results are presented.     

用于加速度计接口电路的新型∑-Δ电压-频率转换器的设计

设计了一种基于Σ-Δ调制器技术的新型电压.频率转换器,可用于加速度计接口电路将模拟电压信号转换成相应的频率输出信号,且其对于恒定输入电压具有稳定的输出频率,具有正负两种转换特性.采用中国电子科技集团二十四所的4μm阱标准CMOS工艺参数对电路进行了模拟仿真.在10V电源电压下,其时钟频率为1.04MHz,输入电压范围为1.5～8.5 V,输出频率范围为40-533 kHz,转换灵敏度约为134 kGz/V,非线性度小于0.08%.仿真结果表明,其可广泛应用于矢量传感器的模数转换接口电路.     

High Precision SAR ADC Using CNTFET for Internet of Things

A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 μW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit. The proposed architecture has high scalability to CNTFET technology and also has higher energy efficiency. We compared the results of CNTFET based SAR ADC with other known architectures and confirm that this proposed SAR ADC can provide higher precision, power efficiency to the Internet of things node.     

Spectral Response Based Calibration Method of Tristimulus Colorimeters

A new method is described to calibrate tristimulus colorimeters for high accuracy color measurements. Instead of traditional lamp standards, modern, high accuracy detector standards are suggested for calibration. After high accuracy absolute spectral response determination of the tristimulus receivers, color (spectral) correction and peak (amplitude) normalization can minimize uncertainties caused by imperfect realizations of the Commission Internationale de l’Eclairage (CIE) color matching functions. As a result of the corrections, stable light sources of different spectral power distributions can be measured with an accuracy dominated by the sub tenths of a percent uncertainty of novel spectral response determinations.