A multilevel metallized DSA MOS masterslice

A new LSI with high-speed capability and high-packing density for computer use has been successfully achieved within a short turnaround time by a new DSA MOS masterslice. Two-level metallization has been accomplished by the use of full plasma processes. The average gate delay time of the new masterslice was improved to 2 ns compared with 3 ns in the case of single-level metallization.     

A high speed molybdenum gate MOS RAM

Describes a high speed 16K molybdenum gate (Mo-gate) dynamic MOS RAM using a single transistor cell. New circuit technologies, including a capacitive-coupled sense-refresh amplifier and a dummy sense circuit, enable the achievement of high speed performance in combination with reduced propagation delay in the molybdenum word line due to the low resistivity. The n-channel Mo-gate process was established by developing an evaporation apparatus and by an improved heat treatment to reduce surface charge density. Ultraviolet photolithography for 2 /spl mu/m patterns and HCl oxidation for 400 /spl Aring/ thick gate oxide are used. The 16K word/spl times/1 bit device is fabricated on a 3.2 mm/spl times/4.0 mm chip. Cell size is 16 /spl mu/m/spl times/16 /spl mu/m Access time is less than 65 ns at V/SUB DD/=7 V and V/SUB BB/=-2 V. Power dissipation is 210 mW at 170 ns read-modify-write (RMW) cycle.     

A UHF MOS tetrode with polysilicon gate

An n-channel high-frequency MOS tetrode has been made using a modified Silicon gate process. Design and processing criteria for obtaining UHF performance are discussed. A feedback capacitance of 5 fF (at 1 mm gate length) and a minimum noise figure of 1.6 db at 800 MHz have been realized.     

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.     

A novel single gate MOS controlled current saturated thyristor

A novel single gate MOS controlled current saturation thyristor (MCST) device is proposed. In the on-state the MCST operates in thyristor-like mode at low anode voltage and enters the IGBT-like mode automatically with increasing anode voltage, offering a low on-state voltage drop and current saturation capability. Simulation results based on 6.5 kV trench devices indicate the turn-off energy loss of the MCST is reduced by over 35% compared to the IGBT. The saturation current density of the MCST is strongly dependent on the on-set voltage of the p ⁺ buffer/n-well junction, leading to its excellent safe operation area (SOA) and making it suitable for high power applications     

A nitride-isolated molybdenum-polysilicon gate electrode for MOS VLSI circuits

A new gate electrode structure is demonstrated. The low-resistive gate electrode consists of a triple layer of molybdenum and polysilicon films isolated with an ultrathin silicon-nitride film, namely MTP-metal/tunneling nitride/polysilicon. The tunneling nitride, which is grown by direct thermal nitridation of silicon, avoids silicidation of molybdenum and diffusion of impurities resulting in a thin SiO2film of good quality. Characteristics of discrete FET's can be designed like those of conventional silicon-gate devices. No instability due to the tun, neling nitride has been observed in both dc and high-speed switching operations. The technique is useful for MOS VLSI circuits.     

A review of gate tunneling current in MOS devices

Gate current in metal–oxide–semiconductor (MOS) devices, caused by carriers tunneling through a classically forbidden energy barrier, is studied in this paper. The physical mechanisms of tunneling in an MOS structure are reviewed, along with the particularities of tunneling in modern MOS transistors, including effects such as direct tunneling, polysilicon depletion, hole tunneling and valence band tunneling and gate current partitioning. The modeling approach to gate current used in several compact MOS models is presented and compared. Also, some of the effects of this gate current in the performance of digital, analog and RF circuits is discussed, and it is shown how new effects and considerations will come into play when designing circuits that use MOSFETs with ultra-thin oxides.     

Induced gate noise in MOS FET's

Input admittance, drain noise and induced gate noise measurements are reported on several MOS FET's of large geometry. A few units show excess gate noise as found earlier by Halladay and van der Ziel. Other units show the gate noise expected from the thermal noise of the channel.     

Shielded silicon gate complementary MOS integrated circuit

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift inC-Vcurve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.     

Postmetallisation annealing of aluminium-silicon gate MOS capacitors

Postmetallisation annealing (PMA) is widely used to reduce midgap interface trap densities in aluminium gate MOS structures. It is shown that the presence of 1% silicon in the aluminium inhibits PMA and that increased PMA times result in an increase rather than a decrease in midgap interface trap densities for AlSi.     

Conduction mechanisms in MOS gate dielectric films

This paper reviews the conduction mechanisms in the gate dielectric films of MOSFETs for VLSI and ULSI technologies. They include Fowler–Nordheim tunneling, internal Schottky (or Pool–Frenkel) effect, two-step (or trap-assisted) tunneling, shallow-trap-assisted tunneling, and band-to-band tunneling. The current transport in the gate dielectric films is manly controlled by film material composition, film processing conditions, film thickness, trap energy level and trap density in the films. In general, for a given gate dielectric film, the current transport behaviors are normally governed by one or two conduction mechanisms.     

DPN MOS绝缘栅氮处理技术

分析了90nm及其以上技术、栅氧化及其氮处理工艺的局限性,强调了等离子体氮处理技术在90nm及其以下技术中的必要性.介绍了应用材料公司DPN MOS绝缘栅氮处理技术,并出示了部分试验数据.     

An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications.     

A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell

A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W.     

A 540 K-transistor CMOS variable-track masterslice

A basic cell structure of p-n-n (a set of one p-channel and two n-channel resistors) is proposed for the cell of a variable-track masterslice (VTM) in order to increase the utilization of logic gates. The masterslice has 180 K p-channel and 360 K n-channel transistors for logic circuitry; it uses 1-3 /spl mu/m double-metal CMOS technology, and has 60 K equivalent (two-input NAND) gates without channel. A small track increment of six or nine allows fine adjustment of the track count in each routing channel. The gate density in p-n-n VTM has been increased by 10 to 30% over a conventional p-n VTM, where p-n represents CMOS pair transistors.     

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Thermally stable, high-quality ultrathin (EOT=13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO/sub 2/ up to 900/spl deg/C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.     

New technique for measuring small MOS gate currents

A new technique is presented for the measurement of small gate currents on MOSFET devices in noisy environments. Hybrid technology is used to build the equivalent of a double-gate FAMOS-type device using two conventional MOSFET devices. Measurements of substrate hot-electron currents are given as an example.     

Sensitive technique for measuring small MOS gate currents

A simple but ultrasensitive method for measuring MOS gate currents down to the attoampere range has been developed. The new technique routinely measures oxide currents in conventional MOSFET structures arising from effects such as hot-electron emission, oxide leakage or tunneling at levels too low to be easily detected by previously available techniques. No FAMOS-type device is required. This technique was used to measure both channel and substrate hot-electron currents. Substrate hot-electron currents measured with the new technique were in excellent agreement with those measured directly.