Design and Realization of a Fully On-Chip High-$Q$ Resonator at 15 GHz on Silicon

We develop and demonstrate an on-chip resonator working at 15 GHz with a high quality factor ( $Q$-factor) of 93.81 while only requiring a small chip size of $hbox{195} muhbox{m} times hbox{195} muhbox{m}$ on Si by using our new design methodology. In our design, unlike previous approaches, we avoid the need for any external capacitance for tuning; instead, we utilize the film capacitance as the capacitor of the LC tank circuit and realize a fully on-chip resonator that shows a strong transmission dip of $≫hbox{30} hbox{dB}$ on resonance as required for telemetric-sensing applications. We present the design, theory, methodology, microfabrication, experimental characterization, and theoretical analysis of these resonators. We also demonstrate that the experimental results are in excellent agreement with the theoretical (both analytical and numerical) results. Based on our proof-of-concept demonstration, such high- $Q$ on-chip resonators hold great promise for use in transmissive telemetric sensors.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

$n$ -SIFT: $n$ -Dimensional Scale Invariant Feature Transform

We propose the $n$ -dimensional scale invariant feature transform ( $n$-SIFT) method for extracting and matching salient features from scalar images of arbitrary dimensionality, and compare this method's performance to other related features. The proposed features extend the concepts used for 2-D scalar images in the computer vision SIFT technique for extracting and matching distinctive scale invariant features. We apply the features to images of arbitrary dimensionality through the use of hyperspherical coordinates for gradients and multidimensional histograms to create the feature vectors. We analyze the performance of a fully automated multimodal medical image matching technique based on these features, and successfully apply the technique to determine accurate feature point correspondence between pairs of 3-D MRI images and dynamic $3{rm D} + {rm time}$ CT data.      

MILC-TFT With High-$kappa$ Dielectrics for One-Time-Programmable Memory Application

In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-channel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high- $kappa$ dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage $V_{rm th} sim -hbox{0.78} hbox{V}$, excellent subthreshold swing $sim !!$ 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.      

Compact, High-$Q$, and Low-Current Dissipation CMOS Differential Active Inductor

This letter presents an improved, compact, and tunable high-Q differential active inductor implemented in Silterra's industry standard 0.18 mum CMOS process. The improved differential active inductor demonstrates a Q ap 1000 at high frequency region. Low-current dissipation is achieved by reusing the current from the differential gyrator for stabilizer and negative impedance circuit. A replica bias circuit has been introduced to allow current-controlled inductance of the improved differential active inductor. Sensitivity of the improved differential active inductor to process variation is also included in this letter.     

High $Q$ -Factor Microrings Using Slightly Etched Rib Waveguides

The paper reports the design, fabrication and characterization of silicon-on-insulator (SOI) microring resonators using shallow etched rib waveguides. The variation of the $Q$-factor of microring resonators as a function of the ring diameter and coupling gap between the input waveguide and the ring is studied. Such structures are fabricated using e-beam lithography and reactive ion etching steps. Propagation loss of shallow etching rib waveguide has been evaluated to 0.8 dB/cm for wavelengths around 1550 nm. With a ring diameter of 100 $mu{rm m}$ and a coupling gap of 450 nm, the measured $Q$ -factor is 35300. These results are matched by 3-D numerical optical modeling.      

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

$C$ -Band Optical 90$^{circ}$ -Hybrids Based on Silicon-on-Insulator 4 $times$ 4 Waveguide Couplers

We demonstrate 4times4 multimode interference couplers in a silicon-on-insulator rib waveguide technology that enable compact integrated fully passive optical 90deg-hybrid devices with operation across the C-band.     

A 100 $mu$ W 128 $times$ 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications

An ultra-low power 128 $times$ 64 pixels vision sensor is here presented, featuring pixel-level spatial contrast extraction and binarization. The asynchronous readout only dispatches the addresses of the asserted pixels in bursts of 80 MB/s, significantly reducing the amount of data at the output. The pixel-embedded binary frame buffer allows the sensor to directly process visual information, such as motion and background subtraction, which are the most useful filters in machine vision applications. The presented sensor consumes less than 100 $muhbox{W}$ at 50 fps with 25% of pixel activity. Power consumption can be further reduced down to about 30 $muhbox{W}$ by operating the sensor in Idle-Mode, thus minimizing the sensor activity at the ouput.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

A Current-Feedback Instrumentation Amplifier With 5 $mu{hbox{V}}$ Offset for Bidirectional High-Side Current-Sensing

This paper describes an instrumentation amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 $mu{hbox{V}}$ , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The instrumentation amplifier was realized in a 0.8 $mu{hbox{m}}$ BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 ${hbox{mm}}^{2}$ .      

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

$B_1$ Homogenization in MRI by Multilayer Coupled Coils

Transmit $B_1^+$ field homogenization in high-field ( ${>}3.0$ T) human magnetic resonance imaging (MRI) is challenging due to radio-frequency wavelength effects. An approach based on appropriately coupling surface coils to a volume coil was investigated. Electromagnetic simulation results demonstrated the feasibility and effectiveness of this method in proton MRI of the human head at 7.0 T.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

Efficient Frequency Doubling of a Low-Power Femtosecond Er-Fiber Laser in BiB$_{3}$ O$_{6}$

BiB₃O₆ (BIBO) crystal has been used for efficient second-harmonic generation (SHG) of a low-power femtosecond Er-fiber laser-amplifier system operating at 56 MHz. At the maximum input power of 65 mW, an internal conversion efficiency of 23% was achieved for SHG at 782 nm, with a pulse duration of 64 fs. A comparison with beta-BaB₂O₄ reveals superior properties of BIBO for such ultrashort-pulse ultra-broadband SHG.     

Nitride-Based Asymmetric Two-Step Light-Emitting Diode With In$_{0.08}$ Ga$_{0.92}$ N Shallow Step

A nitride-based asymmetric two-step light-emitting diode (LED) with $hbox{In}_{0.08} hbox{Ga}_{0.92}hbox{N}$ shallow step was proposed and fabricated. It was found that the low indium content $hbox{In}_{0.08} hbox{Ga}_{0.92}hbox{N}$ layer can significantly enhance phase separation and/or inhomogeneous indium distribution in the active $hbox{In}_{0.27}hbox{Ga}_{0.73}hbox{N}$ layer. It was also found that we can enhance LED output power by a factor of 2.27 by simply inserting an $hbox{In}_{0.08} hbox{Ga}_{0.92}hbox{N}$ shallow step.      

Modeling $R{-}2R$ Segmented-Ladder DACs

Although $R{-}2R$ ladders are commonly used as digital-to-analog converter (DAC) cores, complete equivalent circuits are still missing from the literature for most of the configurations used in practice. In this paper, expressions for the input and output impedances of $R{-}2R$ ladders are derived for current- and voltage-mode operations. In addition, since many DACs use segmentation to reach higher resolutions, the impedance expressions are also obtained for different segmentation schemes. Using these expressions, the existing current-mode model is extended to segmented architectures, and a new equivalent circuit is proposed for voltage-mode designs. This allows modeling the most common $R{-}2R$ DAC designs. Simulation results produced with the proposed models are compared to measurements on two 14-bit $R{-}2R$ DAC prototypes. These results demonstrate how impedance variation with code can limit the static performances of high-resolution converters.