A 220 GHz Single-Chip Receiver MMIC With Integrated Antenna

This letter presents the design and characterization of a 220 GHz microstrip single-chip receiver monolithic microwave integrated circuit (MMIC) with an integrated antenna in a 0.1 mum GaAs metamorphic high electron mobility transistor technology. The receiver MMIC consists of a novel slot-square substrate lens feed antenna, a three-stage low noise amplifier, and a sub-harmonically pumped resistive mixer. The receiver MMIC is mounted on a 12 mm silicon substrate lens which focuses the radiation from the calibration loads to the on-chip antenna through an opening in the backside metallization of the MMIC. The double sideband noise figure of this quasioptical receiver is as low as 8.4 dB (1750 K) at 220 GHz including the losses in the antenna and in the lens. To the best of the authors' knowledge, this work demonstrates the highest integration level versus operating frequency for a MMIC ever published, regardless of technology.     

A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas

In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi     

卷积码在60 GHz芯片间无线互连系统中的性能分析

针对60 GHz芯片间无线互连系统中信号幅度衰落及多径时延,导致信道产生突发性错误引起误码率增大的问题,从编码增益和译码能耗角度研究了该系统中卷积码的性能.根据60 GHz芯片间无线互连系统特点,分析了适用于此场景的CM7.2信道特性以及编码系统接收信噪比.结合信道编码理论,推导了卷积码的临界距离,得到了编码系统的能效衡量标准.在此理论研究的基础上,通过MATLAB对卷积码进行了蒙特卡洛数值仿真,得到了编码增益,进而分析了最大通信距离.通过QuartusⅡ对卷积码进行了电路能耗仿真,得到了编译码能耗,进而分析了临界距离.综合考虑卷积码的编码增益、译码能耗及有效通信距离,提出了可优先采用的编码方案.为60 GHz芯片间无线互连系统以及其他60 GHz近距离无线通信系统提供了纠错编码方面的技术参考.     

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10^-8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.     

CMOS Silicon Receiver Integrated With Ge Detector and Reconfigurable Optical Filter

We demonstrate a complmentary metal–oxide–semiconductor (CMOS)-compatible and widely tunable filter with an integrated germanium detector. The filter uses two stages of sixth-order pole-zero filtering cascaded in a vernier fashion to achieve simultaneous tunability and adjustable passband bandwidth from 25 to 50 GHz tuned over a wavelength range $>$12 nm. The out-of-band crosstalk rejection is $sim$30 dB. The monolithically integrated detector has a bandwidth of 6 GHz. We also demonstrate a modified detector design which showed a bandwidth of 11 GHz/s and responsivity of 0.75 A/W.      

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

Communication Using Antennas Fabricated in Silicon Integrated Circuits

The feasibility of integrating compact antennas and required circuits for implementing wireless interconnections in foundry digital CMOS technologies has been demonstrated. A 3-mm long zigzag dipole antenna on a 20-Omega-cm substrate should have efficiency up to approximately 25% at 24 GHz and cost 1-2 cents. These antennas can be used to implement a radio for 100-kb/s communication up to about 10 m. By lowering the operation frequency to 5.8 GHz and using a monopole structure, which occupies approximately 30% more area, the communication range can be increased by three times or more. This technology, as well as in a true single-chip radio, can be used for intra- and inter-chip data communication, intra- and inter-chip clock distribution, beacons, radars, RFID tags, and contactless high-frequency testing.     

Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism

In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 90-nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing.     

Fundamental Limits and Design Guidelines for Miniaturizing Ultra-Wideband Antennas

Fundamental physical limitations restrict an antenna's performance based on its electrical size. These fundamental limits are of the utmost importance, since the minimum size needed to achieve a particular figure of merit can be determined from them. In this paper, the physical limitations of antennas are reviewed in general, with particular emphasis on impedance matching as it relates to ultra-wideband (UWB) antennas (high-pass response). Additionally, the use of antenna miniaturization techniques to approach these limits is discussed. Using a spiral antenna as an example, guidelines are presented for miniaturizing UWB antennas.     

Radio-Optical Dual-Mode Communication Modules Integrated With Planar Antennas

This paper presents new results on integrated devices for radio and free-space optical dual-mode communication. Two novel hybrid packaging schemes using two different microwave printed antenna designs are presented for the integration of radio-optical front-end circuits on a planar compact printed circuit board with shared electrical and structural components. Full-wave electromagnetic (EM) simulations are presented for antenna optimization to minimize EM interference between the radio and optical circuits. A hybrid radio-optical package design is developed, prototyped, and experimentally studied using a modified quasi-Yagi antenna with split directors to form pads for opto-electronic device integration. Dual-mode link connectivity is investigated in simulations and experiments. A data rate of 2.5 Gb/s is demonstrated for the optical channel despite 15–20-dB signal coupling between the optical and microwave circuits.      

A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems

This paper presents an RF receiver front-end for MB-OFDM-based ultra-wideband (UWB) systems. The receiver occupies only 0.35 mm² in a 0.18 mum CMOS process and consists of a low-noise amplifier, downconverter and a bandpass filter. There are no on-chip inductors and the receiver requires no off-chip matching components. The measured receiver gain is 21 dB, noise figure is less than 6.6 dB, input IIP₃ is -5.6 dBm, and the receiver consumes 19.5 mA from a 2.3 V supply. The receiver covers all the MB-OFDM bands from 3.1 to 8 GHz     

A Fully Differential Monolithic LNA With On-Chip Antenna for a Short Range Wireless Receiver

This letter presents the smallest reported 5 GHz receiver chip (1.3 mm²) with an on-chip antenna in standard 0.13 mum CMOS process. The miniaturization is achieved by placing the circuits inside a meandered antenna. The on-chip antenna is conjugately matched to the low noise amplifier (LNA) over a wide frequency range. The design methodology for co-design of the on-chip antenna and LNA is described. The LNA is completely differential, consumes only 8 mW of power and provides a gain of 21 dB. Design tradeoffs and measurement challenges are given.     

无线系统中的智能天线

本文介绍了智能天线在未来移动通信系统中的重要作用.分别介绍了多波束天线和自适应天线阵,阐明了智能天线的定义、组成.着重介绍了在自适应天线阵通信系统中的时空信号模型、空间信道模型和时空通信理论,比较了智能天线中的智能算法.最后,结合智能天线技术的应用进展,探讨了实现智能天线的难点和发展前景.     

A Hairpin Line Diplexer for Direct Sequence Ultra-Wideband Wireless Communications

A high performance hairpin line diplexer for the direct sequence ultra-wideband communication is designed and implemented. This microstrip diplexer is mainly composed of two hairpin line wideband bandpass filters and a tapped open stub. The design concept is proposed in detail and has been verified by the experimental results of the fabricated diplexer, including the two isolated wideband bandwidths of 3.1-5.0 GHz and 6.02-10 GHz, low insertion loss and high isolation. Experimental results also show a good agreement with the simulated results.     

A Modular Wireless Sensor Platform With Fully Integrated Battery

This paper presents the design and development of a miniaturized, modular, system platform with fully integrated battery for wireless sensor nodes. It uses commercial off-the-shelf components and overcomes many of the limitations that attach to more conventional wireless sensor nodes based on planar vertical stacking of circuit boards. The platform is based around a plastic cubic framework that also acts as a receptacle for the battery. Six printed circuit boards (PCBs), interconnected with flex-PCB, are folded around the six faces of the cube, with two of the PCBs making contact with the two terminals of the battery. The sensor node architecture is partitioned in a modular fashion so that the main node circuit blocks (power, sensors, processing, and communications) are allocated to the individual PCBs on the six faces of the cube. Each of the PCBs has a common edge-connection layout, and each of the flex tapes joining the PCBs is identical in layout, giving a common ldquobusrdquo between the PCBs. This makes it easy to change any of the individual circuit blocks without having to redesign the whole system. The use of a cube also means that the sensors and antenna can each be on an external face of the node instead of being limited to the two external faces typical of planar vertical stacks. The functionality of the platform is verified by the design, assembly, and testing of a four-sensor environment sensing node working at 868 MHz.     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

Reconfigurable Antennas for Advanced Wireless Communications: A Review

Wireless Personal Communications - Modern era of wireless communication relies on the evolution of adaptive antennas. This influences the new age antenna designs to adapt themselves to the changing...     

A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

This paper describes the design of a 2.5-Gb/s burst-mode optical receiver in a 0.18-mum CMOS process. A dual-gain-mode transimpedance amplifier (TIA) with constant damping factor control is proposed to tolerate a wide dynamic range input signal. By incorporating an automatic threshold tracking circuit (ATC), the TIA and limiting amplifier (LA) are dc coupled with feedforward offset cancellation. Dual-band filters are adopted in the ATC for a rapid response time while keeping the tracking error small. By integrating both a TIA and a post-LA in a single chip, the burst-mode receiver provides a conversion gain of 106 dBmiddotOmega in the high gain mode, 97 dBmiddotOmega in the low gain mode, and a -3-dB bandwidth of 1.85 GHz. The measured input sensitivity, overload level, and dynamic range of the optical receiver are -19 dBm, -2 dBm, and 17 dB, respectively. The response time is less than 50 ns. Operating under a single 1.8-V supply, this chip dissipates only 122 mW.