IC卡中薄芯片碎裂失效机理的研究

薄/超薄芯片的碎裂占据IC卡早期失效的一半以上,其失效模式、失效机理亟待深入研究.本文分析了芯片碎裂的失效模式和机理,并结合实际IC卡制造工艺以及IC卡失效分析实例,就硅片减薄、划片、顶针及卡片成型工艺对薄IC芯片碎裂的影响进行深入探讨.     

薄片划片微损伤与芯片断裂强度探讨

超薄圆片的减薄、划片技术是集成电路封装小型化的关键基础工艺技术,随着减薄后化学机械抛光（CMP）、旋转腐蚀、干法刻蚀或干法抛光等释放应力技术被广泛采用,减薄造成的圆片背面损伤几乎为零,所以划片造成的微损伤对芯片断裂强度的影响变得越来越突出。本文分析了影响芯片断裂强度的主要原因,对薄片划片微损伤的来源、危害及解决方法进行了探讨。同时,着重介绍了一种新的激光划片方式,即喷水波导激光（LMJ）划片法。     

中电智能卡有限责任公司(CESC)

正中电智能卡有限责任公司由中电广通股份有限公司和公安部第一研究所等共同投资组建,装备世界最先进的IC卡、模块、多芯片(COB)封装设备和8英寸、12英寸芯片减薄、划片设备,专业生产各种IC卡、模块和大容量卡,同时提供多芯片封装(COB)服务,生产技术及产品质量始终处于领先地位;公司年生产能力为:IC卡60亿张;接触(双界面)和非接触式模块5.1亿块;大容量和TF卡二千万张。     

"魔法"激光划片-MAHOH

划片工艺概述划片工艺隶属于晶圆加工的封装部分,它不仅仅是芯片封装的核心关键工序之一,而且是从圆片级的加工(即加工工艺针对整片晶圆,晶圆整片被同时加工)过渡为芯片级加工(即加工工艺针对单个芯片)的地标性工序。从功能上来看,划片工艺通过切割圆片上预留的切割划道(street),将众多的芯片相互分离开,为后续正式的芯片封装做好最后一道准备。划片工艺的发展历程在最早期,人们通过划片机(Scriber)来进行芯片的切割分离,其过程类似于今天的手工划玻璃,用金刚刀在被切割晶圆的表面刻上一道划痕,然后再通过裂片工艺使晶圆沿划痕分割成单个芯…     

IC卡电子锁芯片CIPH09特性及应用

1.芯片功能特性 CIPH09芯片是IC卡电子密码锁的核心,它具有密码设置、插卡检测、IC卡读写以及插卡开锁等功能.修改密码时,由键盘输入的用户密码不仅被写入密码控制器的24C01A EEPROM中,同时也写入用户手持IC卡中;开锁时,只要将手持IC卡插入IC卡座中即可将电控锁体开启,使用方便,开锁快捷,特别适合老人等记忆力差的人员使用.     

中电智能卡有限责任公司(CESC)

正中电智能卡有限责任公司由中电广通股份有限公司和公安部第一研究所等共同投资组建,装备世界最先进的1C卡、模块、多芯片(COB)封装设备和8英寸、12英寸芯片减薄、划片设备,专业生产各种IC卡、模块和大容量卡,同时提供多芯片封装(COB)服务,生产技术及产品质量始终处于领先地位;公司年生产能力为:IC卡60亿张;接触(双界面)和非接触式模块5.1亿块;大容量和TF卡二千万张。中电智能卡有限责任公司始终坚持追求卓越品质,快速服务客户,持续不断的改     

中电智能卡有限责任公司(CESC)

中电智能卡有限责任公司由中电广通股份有限公司和公安部第一研究所等共同投资组建,装备世界最先进的IC卡、模块、多芯片(COB)封装设备和8英寸、12英寸芯片减薄、划片设备,专业生产各种IC卡、模块和大容量卡,同时提供多芯片封装(COB)服务,生产技术及产品质量始终处于领先地位;公司年生产能力为:IC卡60亿张;接触(双界面)和非接触式模块5.1亿块;大容量和TF卡二千万张。中电智能卡有限责任公司始终坚持追求卓越品质,快速服务客户,持续不断的改进生产技术和服务水平,超越满足用户需求;在信息产业部支持下,公司完成了多项     

非接触IC卡模块封装技术

1、简介非接触式IC卡模块是IC卡的心脏,是通过专业封装技术将IC芯片和引线框架以特定的连接方式组合在一起,由于它是接近芯片尺寸的超薄封装,所以技术难度非常大。我公司于1997年开始研究非接触式IC     

硅的深度反应离子刻蚀切割可行性研究

评估了使用深反应离子刻蚀工艺来进行晶圆的切割,用于替代传统的刀片机械切割方式。结果表明,使用深反应离子刻蚀工艺,晶圆划片道内的硅通过等离子化学反应生成气态副产物被去除,从而避免了芯片侧面的机械损伤。切割后整个晶圆没有出现颗粒沾污,芯片边缘没有崩角以及开裂等损伤。该工艺还可以适用于更窄的划片道切割要求。     

虽有家财万贯 不如金卡傍身(三)

<正> 上篇我们将卡大致分为磁卡、接触式IC卡和非接触式IC卡等几个大类,本篇重点介绍接触式智能IC卡基本的物理特性以及芯片性能。 基本特性 1.基本结构 接触式IC卡的基本构成是依照国际ISO7816提出的ID-1外形尺寸标准,在塑料片基上嵌入集成电路芯片而组成的卡片,示意图如图1所示。其中,电路芯片是IC卡的核心部分,一般采用0.35～0.8μm的CMOS或NMOS工艺制造的超大规模集成电路。芯片电路中,通常包括接口驱动、逻辑加密电控制、译码、存储器,甚至微处理器(CPU)等各种功能电路,示意图如图2所示,而芯片的体积控制在2mm×1mm×0.3mm以内。     

Evaluation of test methods for silicon die strength

The objective of this study is to evaluate the existing test methods of die strength, including widely-accepted three-point and four-point bending tests, and a newly-proposed point-load test by testing silicon die specimens with different surface conditions. It has been reported that there are three factors to influence die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the cutting process), and the weak planes of the crystal lattice of silicon on (1, 1, 0) and (1, −1, 0). In this study, the focus will be on how these factors affect the strength data from these three test methods. Apart from performing these three tests, the roughness of the die surfaces (including the ground, polished and untreated surfaces) measured by atomic force microscopy, and edge chipping conditions by optical microscopy were correlated with strength data obtained from the tests. It was found that the four-point bending test gives the lowest strength data and its independence on the surface condition, due to much domination by the edge chipping. On the other hand, the three-point bending test provides intermediately high strength data, with slight difference between different surface conditions, and some major control by the edge chipping. It was also observed that both bending tests suffer the effect of the grinding-mark direction. By contrast, the point-load test associated with the applied force-maximum stress equation which is proved to be valid for Hertzian contact and, sometimes, required to take into account geometrically nonlinear effect, gives the highest values of strength among these methods. This test not only provides the data which are merely dependent on the surface roughness and free from the edge chipping and grinding-mark direction effects, but also it gives a bi-stress field similar to the temperature loading and provides direct test for dummy or real IC chips. As a result, the point-load test is one of the most adequate test methods for determining the die strength exclusively due to surface roughness effect.     

Experimental study on ultrasonic stress relief for cured SU-8 photoresist layer

The purpose of this work is to reduce the internal stress in cured SU-8 photoresist layer by ultrasonic stress relief technology. The stress relief mechanism of SU-8 photoresist layer was presented. Based on improved Stoney’s formula, a theoretical calculation model for SU-8 internal stress was proposed. Profile method was used to measure the curvature radius of substrate. The effect of ultrasonic stress relief on SU-8 layers was studied by experiments. Meanwhile, some important factors, such as amplitude of vibration, power input and relief time, have been discussed. The values of internal stress before and after the ultrasonic stress relief process were compared. The experimental results show that the internal stress in cured SU-8 layers can be effectively reduced if the proper experimental parameters are chosen.     

Experimental method and FE simulation model for evaluation of wafer probing parameters

Wafer probing technology is a critical testing technology that is used in the semiconductor manufacturing and packaging process. A well-designed probing system must enable low and stable contact resistance when each needle-like probe makes contact with the IC chip-bonding pad. Mechanical contact using excessive probe force causes over-sized scrub marks that may damage the die pad and sizably deform the probe tip. In this paper, an experimental setup of a single tungsten needle probe making contact with an Al pad was employed to investigate the relationships between the overdrive, contact force, and scrub mark length. A three-dimensional computational probing simulation model was developed for analyzing dynamic deformations of the contact phenomena during wafer testing. The mechanical tensile strength of the tungsten needle was tested with a micro-tester to examine the tensile stress-strain relationship. The elastoplastic behaviors of the probe and die were taken into account in the simulation model. The resultant scrub lengths from the simulation were verified against the experimental data. Additional critical data, such as data of the scrub mark sinking on the die surface and the maximum Von-Mises stress level location at the probe tips, can be predicted. The experimental and numerical methods presented here can be used as useful performance evaluation tools to support the choice of suitable probe geometry and wafer probe testing parameters.     

Effect of wafer thinning methods towards fracture strength and topography of silicon die

This paper characterizes die damage resulting from various wafer thinning processes. Die fracture strength is measured using ball breaker test with respect to die surface finish. Further study on surface roughness and topography of each surface finish is obtained by atomic force microscopy (AFM) and scanning electron microscopy (SEM) techniques. Stress relief process with 25 μm removal is able to strengthen 100 μm wafer by 20.4% using chemical wet etch and 75 μm wafer by 36.4% with plasma etch. Relatively, plasma etching shows higher fracture strength and flexibility compared to chemical wet etch. This is due to topography of the finished surface of plasma etch is smoother and rounded, leading to a reduced stress concentration, hence improved fracture strength.     

In situ measurement of mechanical properties of polyimide filmsusing micromachined resonant string structures

Two in situ measurement schemes, using micromachined resonant string structures, for the measurement of the polyimide residual stress and polyimide/metal adhesion durability have been developed. The residual stress of polyimide films, DuPont PI-2555 and PI-2611, have been measured using a bulk micromachined string structure. According to the Rayleigh's method, the resonant frequency of a polyimide string can be related to the film stress. By measuring the resonant frequency of these polyimide strings, the residual stresses have been calculated. The measurement results of various strings have been compared with conventional measurement results, which shows that they are in good agreement. Also, a noble scheme to quantize the adhesion durability between a polyimide film and a metal film has been developed. This scheme is based on a polyimide/metal bimorph string structures, fabricated using a surface micromachining technique, vibrating with an alternating potential. The change of resonance profile of this string structure can be related to the degradation of adhesion strength at the polyimide/metal interface. Various polyimide/gold string structures have been fabricated using a surface micromachining with Cu sacrificial layers, and the resonant qualities have been monitored. Notable changes of resonant Q-factor and resonant frequency, due to the degradation of adhesion between the metal and polyimide, have been observed after 10 ⁸ cycles (string vibration) for the polyimide/gold bimorph strings. The changes of resonant Q-factor and resonant frequency over a time period (vibration cycles) have been monitored     

Monolithic,Hierarchical Surface Reliefs by Holographic Photofluidization of Azopolymer Arrays: Direct Visualization of Polymeric Flows

Hierarchically ordered, monolithic surface reliefs have attracted a great deal of interest due to their applications in advanced photonics and interface sciences. While many impressive achievements in fabrication of such surface reliefs have been made over the last decade, all established methods are still restricted by a number of factors, such as limited control of structural features, inherently induced structural defects, impractically low throughput, and technical barriers caused by mechanical contact. Herein, a deterministic and scalable fabrication of hierarchically ordered, monolithic surface reliefs by holographic photofluidization of azopolymer line arrays is demonstrated. In particular, it is shown that the structural features of monolithic surface reliefs including shapes and modulation heights can be deterministically tunable by adjusting the polarization and irradiation time of the holographic interference pattern. Moreover, by a direct visualization of azopolymeric flow according to the light polarization, a long‐standing question about the origin of surface‐relief‐grating formation on azopolymer film is addressed in terms of polymeric flows. Finally, as proof of concept for the practical application of the obtained hierarchical surface reliefs, dependence of wetting properties on modulating height is demonstrated.     

芯片界面强度对其拆解分层的影响研究

电子产品的大量报废使得废弃线路板大量增加,从而使其作为整体丧失原有功能,但其上的元器件特别是集成芯片重用价值高.在拆解重用过程中,加热解焊是重要工艺,它将对已在一定湿度中吸潮饱和的芯片产生热冲击,进而使芯片中产生热应力及湿应力,塑封芯片可能产生分层.为研究芯片界面强度对分层的影响,首先在内聚力理论指导下,对新旧芯片的铜衬底-模塑料间界面强度通过试验-仿真方法进行测量,荻取断裂能、最大张力位移及剪切强度等参数;然后基于ANSYS软件的内聚力模型,建立基于湿-热综合膨胀系数的仿真模型;在此模型中,研究实际中热、湿的极限工况分别对新、旧芯片的界面处切向变形的影响,进而对拆解策略提供指导.     

Smart cards: present and future applications and techniques

Smart cards, or IC cards, have recently begun to appear in many applications, e.g. banking, telephony and TV decoders. So far their use has been restricted to a set of very specific purposes. However, a smart card contains a microprocessor and a memory, so that it can be used for many functions that are presently performed by other devices, such as papers, keys, purses and also, sometimes, other computers. Smart cards provide a high level of security and enable a new family of information systems to be designed. 100 million IC cards will be manufactured in 1991 throughout the world. The paper is both a survey of the existing technology and an attempt to describe some future possibilities     

高芯片键合质量与高生产率的新型银浆体系的研究

高键合强度与高生产率的银浆体系是芯片实现小型化、轻薄化的基础,本文研发了一种高芯片键合强度的新型银浆体系(银浆B),通过五元素三水平(53)正交实验,探讨了银浆量、点胶高度、芯片键合力、银浆固化时间、固化温度等五因素对芯片键合强度及结构的影响;以及基于实验设计(DOE)和响应曲面分析(RSM)等统计方法,分析了芯片键合的过程,优化了芯片键合过程的固化时间、固化温度和银浆量等参数。采用银浆B体系以及优化的制程参数,使得芯片键合强度制程能力指数(Cpk)从0.56提高到2.8。