Efficient photodiode-waveguide coupling for hybrid integrated optical circuits

A GalnAsP edge-detecting photodiode was coupled with an SiO2-TiO2 single-mode waveguide in a simple hybrid integration scheme. The newly developed edge-detecting photodiode with a window region was used to improve photodiode durability.     

Method for modelling substrate coupling in large chip designs

The authors present a novel method for modelling substrate noise in large mixed-signal SPICE designs. The approach is very efficient and can be applied to large designs with many digital blocks. An example circuit, which cannot be efficiently analysed with any current method, is used to demonstrate this new method     

Modeling and analysis of substrate coupling in integrated circuits

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

基于平板电路的无源互调耦合测试方法

无源互调(PIM)是一个吸引众多领域研究人员的课题,包括卫星、天线和智能终端等。本文提出一个非接触式PIM测量的新思路：使用一个经过近场重构的基片集成缝隙波导(SISW)作为互调信号的激励和接收路径,SISW通过对载波信号的远场抑制和近场测试区的优化,实现了一种针对没有射频端口的样品非线性特性的评估解决方案。该测试平台结合了近场天线的有限辐射特性和多敏度测试区在PIM评估中对收发系统和测试样片的适应性。实验结果表明,该测试方法在稳定性和分辨力方面具有相当大的工程应用潜力。     

Electro-thermal coupling analysis methodology for RF circuits

In this paper an electro-thermal co-simulation methodology suitable for RF circuits is presented. It circumvents traditional transient simulation drawbacks that arise when signals or magnitudes whose frequencies are separated orders of magnitude are present simultaneously in the simulated circuit. The accuracy of the proposed technique is verified experimentally by comparing simulation and measurements of the thermal coupling between an integrated power amplifier (PA) and a differential temperature sensor embedded in the same silicon die, using a 65 nm CMOS technology.     

Efficient CMOS counter circuits

Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.     

Efficient logic architectures for CMOL nanoelectronic circuits

CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. Two new CMOL building blocks using transmission gates have been introduced to obtain efficient combinational and sequential logic for CMOL designs. Compared with the existing CMOL circuits, the proposed CMOL designs based on these blocks can achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capabilities. This work significantly advances the applications of CMOL to actual electronic circuits and systems     

Ground bounce modelling for digital gigascale integrated circuits

In the paper, an analytical model for ground bounce noise evaluation taking into account the interdependence between I_DD switching current and V_DD noise voltage is presented. The model shows the discrepancies from general accepted assumption of independence between the two variables. The main conclusion is that noise calculations using the independence assumption cause an overestimation of the noise levels. The results are verified through realistic simulations and for different technology nodes and accurate analysis of two canonical circuits.     

Input mapping algorithm for modelling of CMOS circuits

An algorithm for mapping every possible input pattern of a complementary metal oxide semiconductor (CMOS) gate to an equivalent set of normalised inputs (inputs which have the same starting point and transition time) is presented. Such an algorithm is required in order to perform analytical modelling of CMOS gates, and the results obtained are very accurate compared to SPICE simulations     

Reverse-voltage protection methods for CMOS circuits

A number of circuit configurations for protection of CMOS circuits against erroneous connections to the surrounding world (e.g. reversal of the supply voltage) are suggested and analyzed. It is found that protection against any permutation of input connections, output connections, and supply voltage connections can be obtained. The design objective is to prevent permanent damage to the chip regardless of how it is connected. It has been found both analytically and experimentally that this design goal can be achieved     

Efficient retiming of large circuits

Retiming, introduced by Leiserson and Saxe (1983, 1991), is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock skew optimization and also presented a fast algorithm for minimum period (minperiod) retiming. Since minperiod retiming may significantly increase the number of flip-flops in the circuit, minimum area (minarea) retiming is an important problem. Minarea retiming is a much harder problem than minperiod retiming, and previous techniques were not capable of handling large circuits in a reasonable time. This work defines the relationship between the Leiserson-Saxe and the ASTRA approaches and utilizes it for efficient minarea retiming of large circuits. The new algorithm, Minaret, uses the same basis as the Leiserson-Saxe approach. The underlying philosophy of the ASTRA approach is incorporated to reduce the number of variables and constraints generated in the problem. This allows minarea retiming of circuits with over 56 000 gates in under 15 min     

Status of device-qualified GaAs substrate technology for GaAsintegrated circuits

A review is presented of the current technical status of large-diameter GaAs crystal growth, the effects of residual impurities, stoichiometric defects and crystalline imperfections on the electrical properties of undoped semi-insulating GaAs, and the effectiveness of Group III and V isovalent, lattice-hardening dopants in yielding dislocation-free, semi-insulating GaAs crystals. Factors related to crystal growth, postgrowth annealing, and the preparation of ultraflat, damage-free GaAs wafers, which can significantly improve the performance and yields of directly implanted devices and monolithic circuits are discussed     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

Efficient method for modelling impulse noise in a communicationsystem

Impulse noise is considered to be one of the most damaging impairments in data communications. Based on measurements and the corresponding statistical modelling, an efficient and simple simulation model is proposed and its statistical analysis is outlined