MOSFET的驱动保护电路的设计与应用

率场效应晶体管由于具有诸多优点而得到广泛的应用;但它承受短时过载的能力较弱,使其应用受到一定的限制。分析了MOSFET器件驱动与保护电路的设计要求;计算了MOSFET驱动器的功耗及MOSFET驱动器与MOS-FET的匹配;设计了基于IR2130驱动模块的MOSFET驱动保护电路。该电路具有结构简单,实用性强,响应速度快等特点。在驱动无刷直流电机的应用中证明,该电路驱动能力及保护功能效果良好。     

A three-terminal intelligent power MOSFET with built-in reversebattery protection for automotive applications

An intelligent power MOSFET with built-in reverse battery protection, which is important for automotive power switches, has been developed. The protection is accomplished by integrating an additional power MOSFET in series with a power MOSFET and the control circuit of the additional power MOSFET. The reverse battery protection is achieved without using external control signals. The positive drain breakdown voltage for the proposed MOSFET is 71 V and the negative drain current at a drain voltage of -16 V is only -750 μA. The on-state resistance is 170 mΩ. This new intelligent power MOSFET can replace the conventional three-terminal power MOSFET's used in automotive applications     

A simple and versatile overcurrent protection circuit for power MOSFETs

This paper proposes an overcurrent protection (OCP) circuit for power MOSFETs employed in low voltage power converters. The proposed configuration requires only discrete components with a gate driver IC and uses the voltage drop across the device for overcurrent detection. It can operate independently in cycle-by-cycle shutdown and multiple cycle shutdown modes. In coordination with a micro-controller based driver IC input signal generator and controller, the proposed OCP circuit can also operate in a single cycle latch-up and hiccup OCP modes. The performance of the proposed scheme is evaluated experimentally at both, hard and soft fault conditions. By experimentation, it is shown that the proposed circuit can operate in various protection modes and capable of protecting a MOSFET in both, hard and soft fault conditions.     

A physics-based MOSFET noise model for circuit simulators

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements     

MOSFET modeling for circuit simulation

An overview of MOSFET modeling for circuit simulation is presented. After discussing some of the implications of analog and low-power applications, the history of the MOS models commonly used in SPICE-like circuit simulators is presented, followed by a discussion of the evolution of strategies for modeling the geometry dependence of MOSFET characteristics. The growth of complexity and requirements for future MOS models are also considered     

基于MOSFET设计优化的功率驱动电路

在分析了功率MOSFET其结构特性的基础上,讨论驱动电路的设计,从而优化MOSFET的驱动性能,提高设计的可靠性。     

基于MOSFET设计优化的功率驱动电路

在分析了功率MOSFET结构特性的基础上,讨论驱动电路的设计,从而优化MOSFET的驱动性能,提高设计的可靠性。     

A novel scheme for protection of power semiconductor devicesagainst short circuit faults

Power semiconductor devices find wide application in modern power electronic converters. Protection of these devices against overload/short circuit conditions is of paramount importance. Present day protection topologies employing different circuits have invariably one main drawback in that the fault current reaches the set value before action is initiated to trip the system. This poses a severe stress on the device. Hence an adequate safety margin has to be necessarily provided to prevent excessive device stresses and care has to be taken to see that the device is operated well within its safe operating areas. The present paper proposes a method wherein the slope or rate of rise of the fault current is detected and once the slope exceeds the set reference, action is initiated to trip the system much before the fault current reaches dangerous levels. The method provides a fast means of detection of overload and short circuit currents and can be conveniently adopted for the protection of devices in power transistor/IGBT based inverters against short circuited load conditions or shoot through faults. The possible reduction of stresses in the power devices are also highlighted     

Design of LIGBT protection circuit for smart power integration

Development of a monolithic power integrated circuit by making the lateral insulated gate bipolar transistor (IGBT) the main switching device is a current topic. The overcurrent protection scheme is usually necessary to be built as part of the function in such a power integrated circuit. The protection circuit requires distinguishing various fault conditions and reacting differently based on the device safe operating area (SOA) limitation. At the same time, the protection circuit should also be relatively concise and suitable for integration. In this paper, a concise circuit suitable for integration and with gate drive capability is proposed to provide the complete function of overcurrent SOA protection for the LIGBT. The operational principle was described in detail and the circuit performance was verified with experimental results from both the discrete circuit and the fabricated LIGBT integrated circuit     

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.     

低功耗SRAM掉电保护电路

通常,SRAM的后备电池客量较小,它们的待机工作电流(芯片使能“禁止”)一般也很小,几个μA至几十个μA之间,实际要求在系统断电后,后备电池能够工作的时间越长越好,以保证长期保持SRAM的内容。这样,设计一个工作电流极小的SRAM保护电路,就显得尤其重要。一般常用SRAM掉电保护电路,如高性能的MAX691A,典型工作电流仅30μA。但是,就SRAM而言,具有更低功耗的掉电保护电路才是至关重要的。     

A high-performance planar power MOSFET

Design and experimental realization of a 450-V, 0.75-Ω DMOS power transistor are discussed. Optimization criteria are evaluated for the control of parasitic elements of the planar diffused design.     

A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies

A novel power supply protection clamp is presented which incorporates feedback techniques to improve ESD and normal operational mode behavior. The design uses a short duration RC trigger, which enables the clamp to tolerate very fast power supply ramp rates and exhibit reduced area and leakage. The design is built in a 90 nm CMOS technology with fully salicided source/drain regions.     

A new MOS-gate bipolar transistor for power switches

A new monolithic integrated power device, the MOS-gate transistor (MGT), which consists of a bipolar transistor for an output stage and two MOSFET's for a driver stage, has been investigated. The purpose of the study was to obtain a power switch having characteristics of an easy drive, a short turn-off time, and a high current density. The developed device structure featured the integration of three elements into a small cell from a large number of which the MGT chip was constructed. This device had no parasitic thyristor, making it free from the latchup phenomenon. Unit MGT devices with a blocking voltage of 400-500 V were fabricated. A high current density of 90 A/cm²at a collector-emitter voltage of 2 V and a short turn-off time of less than 1 µs were obtained. The MGT devices, which contained 36 cells, were fabricated with chip sizes of 5 × 5 mm. They exhibited a blocking voltage of 500 V, on-state voltage of 2.3 V at a current of 10 A, and turn-off time of 0.5 µs at 150°C.     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

Small-signal MOSFET models for analog circuit design

Presents first-order large-signal MOSFET models and derives corresponding small-signal models. The parameters of the small-signal models are related to operating-point bias and to the parameters of the IC process used to fabricate the device. The impact upon small-signal performance of many second-order effects present in small-geometry MOSFETs is explored. A representative analog circuit, fabricated with a 1 /spl mu/m feature-size NMOS technology, is analyzed using the small-signal models derived. Results of approximate analysis, without the use of computer aids, are compared with detailed computer simulation results.     

An improved MOSFET model for circuit simulation

Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model     

An equivalent circuit characterization of power MOSFET accounting for high field and high frequency effects

An equivalent circuit model for analyzing the AC characteristics of power VDMOS transistors is presented. The model accounts for high field and saturation effects. This is achieved by incorporating dependent voltage and current sources in the device model. Results are given for the AC characteristics of a POLYFET F2001 Power VDMOSFET rated with a drain current of 1.4A, power out of 2.5W at 1GHz. The linear, quasi-saturation and saturation regions of the IV characteristics are accounted for in the analysis. The small signal device parasitics are extracted through s-parameter methods. The s-parameter results were used to extract the frequency dependent parasitics including parasitic capacitances, inductances and transconductances.     

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψ_s) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.     

A large-area power MOSFET designed for low conduction losses

A new power MOSFET has been fabricated that conducts 75 A with an on-state resistance of 0.012 Ω and blocks 60 V. The device may be used as a low-loss synchronous rectifier in efficient high-frequency power supplies or as a high-current power switch in applications such as emitter switching. The device design criteria include obtaining the largest possible fraction of the ideal blocking voltage and obtaining the minimum on-State resistance. Efficient utilization of the device area requires smaller feature size and shallower junction depths for low-voltage power MOSFET's than for high-voltage ones. The device reported on is 300 mils on a side and contains over 60 000 MOSFET cells in parallel. It has a gate width of more than 4 m. This device is larger and more complex than any previously reported power MOSFET. It provides an example of how power device processing techniques are approaching those of LSI circuit technology.