反馈式ECL记忆门的记忆性能和移位计数器

经过数学论证表明,改进反馈式ECL(MFECL)门可在二个状态中任一态保持稳定,所以认为MFECL门就是一种ECL记忆门或D锁存器.提出了一种由两个ECL记忆门组成的ECL主从D触发器.在上述理论基础上,利用此主从D触发器设计出5进制移位型计数器.经过计算机模拟上述电路,验证了理论和电路的正确性.     

SEU/SET加固D触发器的设计与分析

针对D触发器的抗单粒子辐射效应加固,提出了一种新型的保护门触发器(GGFF)设计,使用两个保护门锁存器串接成主从触发器.通过Spice仿真验证了GGFF抗SEU/SET的能力,通过比较和分析,证明GGFF对于具有同样抗SEU/SET能力的时间采样触发器(TSFF),在电路面积和速度上占据明显优势.     

一种单锁存器CMOS静态D触发器的设计

提出了一种只使用单锁存器的ＣＭＯＳ静态Ｄ触发器结构．由于它比普通的主从型Ｄ触发器少一个锁存器,故所需的管子数少,从而节省了面积．该单锁存器型Ｄ触发器还具有对时钟上升时间不敏感的优点     

微波宽带单片集成电路二分频器的设计与实现

采用D触发器进行分频,设计了基于主从D触发器的1:2分频器,该分频器主要由输入缓冲电路、分频器内核、输出缓冲电路和电流偏置电源四个模块组成.HBT工艺具有速度快、相位噪声低的优点,采用HBT工艺,成功地设计了输入频率范围为50 MHz～7 GHz的静态二分频器.测试结果表明,该分频器在输入频率为3.7 GHz,输入-20 dBm功率时,输出功率4 dBm;电源电压5 V,工作电流85 mA,芯片尺寸为0.85 mm×0.85 mm.     

CMOS电荷泵锁相环中鉴频鉴相器的研究与设计

介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较。通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD。电路设计基于TSMC公司的0.18μm CMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2GHz以上频率的应用环境下。相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景。     

主从型D触发器的无效功耗分析

对主从型 D触发器的功能及时序进行分析 ,证明了该类型触发器无效功耗的存在 ;文章建立了无效功耗的数学模型 ,并通过对典型应用电路的理论推导和计算机模拟 ,验证了这一结论的正确性。分析无效功耗的目的是为了采取措施消除其影响 ,文中提出的数学模型对低功耗 VL SI设计有着重要的价值。     

触发器教学中反馈概念的应用

触发器是数字电路中一个很重要的器件,也是时序逻辑电路的基本组成单元,与门电路比较触发器的特点是具有记忆功能.反馈是模拟电路中的一个重要概念,也是模拟电路中的一个重要内容.文章从反馈的角度先分析了触发器的记忆功能的实质,然后又讨论了触发器转换中反馈的作用,给出了触发器转换过程中功能的扩展是依靠反馈来实现的.     

高性能双模前置分频器设计

提出了一种新颖的分频器设计方案,在高频段采用改进的CMOS源耦合逻辑(SCL)结构的主从D触发器进行分频,以满足高速要求;在低频段采用自锁存的D触发器进行分频.这种结构的D触发器不但具有锁存功能,而且所需的管子比主从式D触发器要少,以满足低功耗和低噪声要求.从而使总体电路实现高速、低功耗、低噪声要求.基于TSMC的0.18 μmCMOS工艺,利用Cadence Spectre工具进行仿真.该分频器最高工作频率可达到5 GHz,在27 ℃、电源电压为1.8 V、工作频率为5 GHz时,电路的功耗仅4.32 mW.     

能量回收技术在D触发器上的应用

将能量回收技术应用于灵敏放大器型D触发器(SAERD),该电路采用单相正弦时钟,用来回收时钟端的能量,对于触发器的内部节点和存储单元仍采用恒定电源。在时钟频率为100～300MHz时,时钟端的功耗较输入方波时平均节省约80%。在SMIC0.13μm工艺下将SAERD应用于一款函数发生器,并与传统主从型D触发器(MSD)实现的电路进行功耗比较。仿真结果显示,时钟频率为200MHz时,功耗节省高达17.1%。     

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。     

New ECL gate in BiFET process

An ECL gate is implemented as a combination of bipolar and MOS circuits in a BiFET process is presented. The resulting ECL gate exhibits an improved speed-power product over circuits presented in the past. Owing to its reduced power consumption this gate allows a higher level of integration for ECL. The process used is standard BiCMOS.<>     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

High-performance bipolar technology for improved ECL power delay

A new shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances. Emitter-coupled logic (ECL) ring-oscillator measurements demonstrate a significant performance leverage, where a delay of 75 ps is obtained at a power of 1.5 mW per gate (power-delay product of 112 fJ ), an improvement of 17% from the nonbutted case. More conventional nonbutted devices have been fabricated with dopant profiles tailored to reduce intrinsic and extrinsic capacitances. These high-performance designs achieve ECL gate delays as small as 26 ps at 5.3 mW, comparable to the fastest ECL delays reported to date     

An ECL gate with improved speed and low power in a BiCMOS process

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible     

A 209 K-transistor ECL gate array with RAM

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V/sub cc/ power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.<>     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

An emitter-coupled logic (ECL) gate with an AC-coupled active pull-down emitter-follower stage that gives high speed at lower power is described. Significant reduction of the speed-power product can be achieved over the conventional ECL gate. The speed/power advantages of the circuit have been demonstrated in a double-poly, trench-isolated, self-aligned bipolar process with 0.8- mu m (mask) emitter width. Unloaded gate delays of 21 ps at 4.1 mW/gate, 23 ps at 2.1 mW/gate, and 35 ps at 1.1 mW/gate have been measured.<>     

Fault modelling of ECL devices

Logic behaviour of an ECL OR/NOR gate under different physical faults is examined. It is shown that the conventional stuck-at fault modelling may be inadequate for obtaining a sufficiently high fault coverage. A new augmented stuck-at fault model is presented which provides a better coverage of physical failures.<>     

High-speed divider using GaAs ECL/CML gate array

An ECL/CML gate array using GaAs/AlGaAs heterojunction bipolar transistors is reported for the first time. The gate array has up to 12 programmable inputs and outputs. A divide-by-eight circuit configured on this array has been clocked at 3.1 GHz.<>