共查询到20条相似文献,搜索用时 93 毫秒
1.
提高静态随机存储器(SRAM)的抗单粒子能力是当前电子元器件抗辐射加固领域的研究重点之一。体硅CMOS SRAM不作电路设计加固则难以达到较好抗单粒子能力,作电路设计加固则要在芯片面积和功耗方面做出很大牺牲。为了研究绝缘体上硅(SOI)基SRAM芯片的抗单粒子翻转能力,突破了SOI CMOS加固工艺和128kb SRAM电路设计等关键技术,研制成功国产128kb SOI SRAM芯片。对电路样品的抗单粒子摸底实验表明,其抗单粒子翻转线性传输能量阈值大于61.8MeV/(mg/cm^2),优于未做加固设计的体硅CMOS SRAM。结论表明,基于SOI技术,仅需进行器件结构和存储单元的适当考虑,即可达到较好的抗单粒子翻转能力。 相似文献
2.
3.
4.
本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上(HIRLF)研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。 相似文献
5.
A novel SEU hardened 10T PD SOI SRAM cell is proposed.By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors,this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU,where the ion affects the single transistor.Through analysis of the upset mechanism of this novel cell,SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references.To achieve this,the new cell adds four transistors and has a 43.4%area overhead and performance penalty. 相似文献
6.
7.
8.
PDSOI CMOS SRAM单元的临界电荷(Critical Charge)是判断SRAM单元发生单粒子翻转效应的依据.利用针对1.2μm抗辐照工艺提取的PDSOI MOSFET模型参数,通过HSPICE对SRAM 6T存储单元的临界电荷进行了模拟,指出了电源电压及SOI MOEFET寄生三极管静态增益β对存储单元临界电荷的影响,并提出了在对PDSOI CMOS SRAM进行单粒子辐照实验中,电源电压的最恶劣偏置状态应为电路的最高工作电压. 相似文献
9.
10.
将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较. 相似文献
11.
Mukhopadhyay S. Keunwoo Kim Ching-Te Chuang 《Electron Devices, IEEE Transactions on》2008,55(1):152-162
Ultrathin-body fully depleted silicon-on-insulator (UTB FD/SOI) devices have emerged as a possible candidate in sub-45-nm technologies and beyond. This paper analyzes leakage and stability of FD/SOI 6T SRAM cell and presents a device design and optimization strategy for low-power and stable SRAM applications. We show that large variability and asymmetry in threshold-voltage distribution due to random dopant fluctuation (RDF) significantly increase leakage spread and degrade stability of FD/SOI SRAM cell. We propose to optimize FD devices using thinner buried oxide (BOX) structure and lower body doping combined with negative back-bias or workfunction engineering in reducing the RDF effect. Our analysis shows that thinner BOX and cooptimization of body doping and back biasing are efficient in designing low-power and stable FD/SOI SRAM cell in sub-45-nm nodes. 相似文献
12.
介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验. 相似文献
13.
介绍在部分耗尽绝缘体上硅(PD SOI)衬底上形成的抗辐射128kb静态随机存储器.在设计过程中,利用SOI器件所具有的特性,对电路进行精心的设计和层次化版图绘制,通过对关键路径和版图后全芯片的仿真,使得芯片一次流片成功.基于部分耗尽SOI材料本身所具有的抗辐射特性,通过采用存储单元完全体接触技术和H型栅晶体管技术,不仅降低了芯片的功耗,而且提高了芯片的总体抗辐射水平.经过测试,芯片的动态工作电流典型值为20mA@10MHz,抗总剂量率水平达到500krad(Si),瞬态剂量率水平超过2.45×1011 rad(Si)/s.这些设计实践必将进一步推动PD SOI CMOS工艺的研发,并为更大规模抗辐射电路的加固设计提供更多经验. 相似文献
14.
Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm2 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices. 相似文献
15.
Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and VDD for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem 相似文献
16.
17.
对0.13μm部分耗尽SOI工艺的抗辐射特性进行了研究.首先通过三维仿真研究了单粒子事件中的器件敏感区域,随后通过实验分析了器件的总剂量效应.三维仿真研究了离子入射位置不同时SOI NMOS器件的寄生双极效应和电荷收集现象,结果表明,离子入射在晶体管的体区和漏区时,均可以引起较大水平的电荷收集.对SRAM单元的单粒子翻转效应(SEU)进行了仿真,结果表明,体区和反偏的漏区都是翻转的敏感区域.通过辐照实验分析了器件的总剂量效应,在该工艺下对于隐埋氧化层,关断状态是比传输门状态更劣的辐射偏置条件. 相似文献
18.
Hirano Y. Maeda S. Matsumoto T. Nii K. Iwamatsu T. Yamaguchi Y. Ipposhi T. Kawashima H. Maegawa S. Inuishi M. Nishimura T. 《Electron Devices, IEEE Transactions on》2001,48(12):2816-2822
Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM were obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint 相似文献
19.
Liu C.C. Tiwari S. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(3):207-211
Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits. 相似文献
20.
Shahidi G.G. Anderson C.A. Chappell B.A. Chappell T.I. Comfort J.H. Davari B. Dennard R.H. Franch R.L. McFarland P.A. Neely J.S. Ning T.H. Polcari M.R. Warnock J.D. 《Electron Devices, IEEE Transactions on》1994,41(12):2405-2412
An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, CL=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained 相似文献